/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <misc.h>
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#include <power-domain-uclass.h>
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#include <asm/arch-tegra/bpmp_abi.h>
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#define UPDATE BIT(0)
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#define ON BIT(1)
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static int tegra186_power_domain_common(struct power_domain *power_domain,
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bool on)
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{
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struct mrq_pg_update_state_request req;
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int on_state = on ? ON : 0;
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int ret;
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req.partition_id = power_domain->id;
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req.logic_state = UPDATE | on_state;
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req.sram_state = UPDATE | on_state;
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/*
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* Drivers manage their own clocks so they don't get out of sync, and
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* since some power domains have many clocks, only a subset of which
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* are actually needed depending on use-case.
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*/
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req.clock_state = UPDATE;
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ret = misc_call(power_domain->dev->parent, MRQ_PG_UPDATE_STATE, &req,
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sizeof(req), NULL, 0);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int tegra186_power_domain_on(struct power_domain *power_domain)
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{
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debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__,
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power_domain, power_domain->dev, power_domain->id);
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return tegra186_power_domain_common(power_domain, true);
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}
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static int tegra186_power_domain_off(struct power_domain *power_domain)
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{
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debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__,
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power_domain, power_domain->dev, power_domain->id);
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return tegra186_power_domain_common(power_domain, false);
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}
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struct power_domain_ops tegra186_power_domain_ops = {
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.on = tegra186_power_domain_on,
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.off = tegra186_power_domain_off,
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};
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U_BOOT_DRIVER(tegra186_power_domain) = {
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.name = "tegra186_power_domain",
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.id = UCLASS_POWER_DOMAIN,
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.ops = &tegra186_power_domain_ops,
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};
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