/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "../common/ngpixis.h"
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#include "corenet_ds.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard (void)
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{
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u8 sw;
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struct cpu_type *cpu = gd->arch.cpu;
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#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
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defined(CONFIG_TARGET_P5040DS)
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unsigned int i;
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#endif
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static const char * const freq[] = {"100", "125", "156.25", "212.5" };
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printf("Board: %sDS, ", cpu->name);
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
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sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
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sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("Promjet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else
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printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
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/* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES Reference Clocks: ");
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#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
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defined(CONFIG_TARGET_P5040DS)
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sw = in_8(&PIXIS_SW(5));
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for (i = 0; i < 3; i++) {
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unsigned int clock = (sw >> (6 - (2 * i))) & 3;
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printf("Bank%u=%sMhz ", i+1, freq[clock]);
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}
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#ifdef CONFIG_TARGET_P5040DS
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/* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
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sw = in_8(&PIXIS_SW(9));
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printf("Bank4=%sMhz ", freq[sw & 3]);
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#endif
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puts("\n");
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#else
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sw = in_8(&PIXIS_SW(3));
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/* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
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/* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
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/* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
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printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
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printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
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printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
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#endif
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return 0;
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}
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int board_early_init_f(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/*
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* P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
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* disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
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* the noise introduced by these unterminated and unused clock pairs.
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*/
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setbits_be32(&gur->ddrclkdr, 0x001B001B);
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
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return 0;
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}
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#define NUM_SRDS_BANKS 3
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int misc_init_r(void)
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{
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serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 actual[NUM_SRDS_BANKS];
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unsigned int i;
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u8 sw;
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#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
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defined(CONFIG_TARGET_P5040DS)
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sw = in_8(&PIXIS_SW(5));
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for (i = 0; i < 3; i++) {
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unsigned int clock = (sw >> (6 - (2 * i))) & 3;
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switch (clock) {
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case 0:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
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break;
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case 1:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
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break;
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case 2:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
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break;
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default:
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printf("Warning: SDREFCLK%u switch setting of '11' is "
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"unsupported\n", i + 1);
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break;
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}
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}
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#else
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/* Warn if the expected SERDES reference clocks don't match the
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* actual reference clocks. This needs to be done after calling
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* p4080_erratum_serdes8(), since that function may modify the clocks.
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*/
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sw = in_8(&PIXIS_SW(3));
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actual[0] = (sw & 0x40) ?
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SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
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actual[1] = (sw & 0x20) ?
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SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
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actual[2] = (sw & 0x10) ?
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SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
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#endif
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
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if (expected != actual[i]) {
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printf("Warning: SERDES bank %u expects reference clock"
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" %sMHz, but actual is %sMHz\n", i + 1,
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serdes_clock_to_string(expected),
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serdes_clock_to_string(actual[i]));
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}
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}
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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fsl_fdt_fixup_dr_usb(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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return 0;
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}
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