/*
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* SPL specific code for Compulab CM-T54 board
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*
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* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
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*
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* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/emif.h>
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const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
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#if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
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.sdram_config_init = 0x618522B2,
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.sdram_config = 0x618522B2,
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#elif defined(CONFIG_DRAM_2G)
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.sdram_config_init = 0x618522BA,
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.sdram_config = 0x618522BA,
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#endif
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.sdram_config2 = 0x0,
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.ref_ctrl = 0x00001040,
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.sdram_tim1 = 0xEEEF36F3,
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.sdram_tim2 = 0x348F7FDA,
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.sdram_tim3 = 0x027F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x1007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0030400B,
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.emif_ddr_phy_ctlr_1 = 0x0034400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x40000305,
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};
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const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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#ifdef CONFIG_DRAM_2G
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.dmm_lisa_map_2 = 0x80740300,
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#elif defined(CONFIG_DRAM_1G)
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.dmm_lisa_map_2 = 0x80640300,
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#elif defined(CONFIG_DRAM_512M)
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.dmm_lisa_map_2 = 0x80500100,
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#endif
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.dmm_lisa_map_3 = 0x00000000,
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.is_ma_present = 0x1,
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};
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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{
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*regs = &emif_regs_ddr3_532_mhz_cm_t54;
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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{
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*dmm_lisa_regs = &lisa_map_cm_t54;
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}
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