/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_INTEL_REGS_H
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#define __ASM_INTEL_REGS_H
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/* Access the memory-controller hub */
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_BASE_SIZE 0x8000
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#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
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#define MCHBAR_PEI_VERSION 0x5034
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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#define MCH_PKG_POWER_LIMIT_HI 0x59a4
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#define MCH_DDR_POWER_LIMIT_LO 0x58e0
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#define MCH_DDR_POWER_LIMIT_HI 0x58e4
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/* Access the Root Complex Register Block */
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#define RCB_BASE_ADDRESS 0xfed1c000
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#define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg))
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#define SOFT_RESET_CTRL 0x38f4
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#define SOFT_RESET_DATA 0x38f8
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#endif
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