/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CMOS_LAYOUT_H
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#define __CMOS_LAYOUT_H
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/*
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* The RTC internal registers and RAM is organized as two banks of 128 bytes
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* each, called the standard and extended banks. The first 14 bytes of the
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* standard bank contain the RTC time and date information along with four
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* registers, A - D, that are used for configuration of the RTC. The extended
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* bank contains a full 128 bytes of battery backed SRAM.
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*
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* For simplicity in U-Boot we only support CMOS in the standard bank, and
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* its base address starts from offset 0x10, which leaves us 112 bytes space.
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*/
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#define CMOS_BASE 0x10
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/*
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* The file records all offsets off CMOS_BASE that is currently used by
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* U-Boot for various reasons. It is put in such a unified place in order
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* to be consistent across platforms.
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*/
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/* stack address for S3 boot in a FSP configuration, 4 bytes */
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#define CMOS_FSP_STACK_ADDR CMOS_BASE
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#endif /* __CMOS_LAYOUT_H */
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