#ifndef _ASM_CPU_SH7706_H_
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#define _ASM_CPU_SH7706_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000000D
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/* MMU and Cache control */
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#define MMUCR 0xFFFFFFE0
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#define CCR 0xFFFFFFEC
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/* PFC */
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#define PACR 0xA4050100
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#define PBCR 0xA4050102
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#define PCCR 0xA4050104
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#define PETCR 0xA4050106
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/* Port Data Registers */
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#define PADR 0xA4050120
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#define PBDR 0xA4050122
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#define PCDR 0xA4050124
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/* BSC */
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#define FRQCR 0xffffff80
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#define BCR1 0xffffff60
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#define BCR2 0xffffff62
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#define WCR1 0xffffff64
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#define WCR2 0xffffff66
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#define MCR 0xffffff68
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/* SDRAM controller */
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#define DCR 0xffffff6a
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#define RTCSR 0xffffff6e
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#define RTCNT 0xffffff70
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#define RTCOR 0xffffff72
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#define RFCR 0xffffff74
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#define SDMR 0xFFFFD000
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#define CS3_R 0xFFFFE460
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/* SCIF */
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#define SCSMR_2 0xA4000150
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#define SCIF0_BASE SCSMR_2
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/* Timer */
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#define TMU_BASE 0xFFFFFE90
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/* On chip oscillator circuits */
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#define WTCNT 0xFFFFFF84
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#define WTCSR 0xFFFFFF86
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#endif /* _ASM_CPU_SH7706_H_ */
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