#ifndef _ASM_CPU_SH7269_H_
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#define _ASM_CPU_SH7269_H_
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/* Cache */
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#define CCR1 0xFFFC1000
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#define CCR CCR1
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/* SCIF */
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#define SCSMR_0 0xE8007000
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#define SCIF0_BASE SCSMR_0
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#define SCSMR_1 0xE8007800
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#define SCIF1_BASE SCSMR_1
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#define SCSMR_2 0xE8008000
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#define SCIF2_BASE SCSMR_2
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#define SCSMR_3 0xE8008800
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#define SCIF3_BASE SCSMR_3
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#define SCSMR_7 0xE800A800
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#define SCIF7_BASE SCSMR_7
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/* Timer(CMT) */
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#define CMSTR 0xFFFEC000
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#define CMCSR_0 0xFFFEC002
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#define CMCNT_0 0xFFFEC004
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#define CMCOR_0 0xFFFEC006
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#endif /* _ASM_CPU_SH7269_H_ */
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