/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef m5253_h
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#define m5253_h
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/****************************************************************************/
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/*
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* PLL Module (PLL)
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*/
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/* Register read/write macros */
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#define PLL_PLLCR (0x000180)
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#define SIM_RSR (0x000000)
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#define SIM_SYPCR (0x000001)
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#define SIM_SWIVR (0x000002)
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#define SIM_SWSR (0x000003)
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#define SIM_MPARK (0x00000C)
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/* Bit definitions and macros for RSR */
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#define SIM_RSR_SWTR (0x20)
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#define SIM_RSR_HRST (0x80)
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/* Register read/write macros */
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#define CIM_MISCCR (0x000500)
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#define CIM_ATA_DADDR (0x000504)
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#define CIM_ATA_DCOUNT (0x000508)
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#define CIM_RTC_TIME (0x00050C)
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#define CIM_USB_CANCLK (0x000510)
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/* Bit definitions and macros for MISCCR */
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#define CIM_MISCCR_ADTA (0x00000001)
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#define CIM_MISCCR_ADTD (0x00000002)
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#define CIM_MISCCR_ADIE (0x00000004)
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#define CIM_MISCCR_ADIC (0x00000008)
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#define CIM_MISCCR_ADIP (0x00000010)
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#define CIM_MISCCR_CPUEND (0x00000020)
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#define CIM_MISCCR_DMAEND (0x00000040)
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#define CIM_MISCCR_RTCCLR (0x00000080)
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#define CIM_MISCCR_RTCPL (0x00000100)
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#define CIM_MISCCR_URIE (0x00000800)
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#define CIM_MISCCR_URIC (0x00001000)
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#define CIM_MISCCR_URIP (0x00002000)
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/* Bit definitions and macros for ATA_DADDR */
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#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2)
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#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18)
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/* Bit definitions and macros for ATA_DCOUNT */
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#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF))
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#endif /* m5253_h */
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