/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Rockchip Audio Delta-sigma Digital Converter driver
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*
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* Copyright (C) 2023 Rockchip Electronics Co., Ltd
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*
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*/
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#ifndef _RK_DSM_H
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#define _RK_DSM_H
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#define DACVUCTL 0x0000
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#define DACVUCTIME 0x0004
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#define DACDIGEN 0x0008
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#define DACCLKCTRL 0x000c
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#define DACINT_DIV 0x0014
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#define DACSCLKRXINT_DIV 0x0020
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#define DACPWM_DIV 0x0024
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#define DACPWM_CTRL 0x0028
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#define DACCFG1 0x0044
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#define DACMUTE 0x0048
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#define DACMUTEST 0x004c
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#define DACVOLL0 0x0050
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#define DACVOLL1 0x0054
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#define DACVOLL2 0x0058
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#define DACVOLL3 0x005c
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#define DACVOLR0 0x0060
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#define DACVOLR1 0x0064
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#define DACVOLR2 0x0068
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#define DACVOLR3 0x006c
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#define DACVOGP 0x0070
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#define DACRVOLL0 0x0074
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#define DACRVOLL1 0x0078
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#define DACRVOLL2 0x007c
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#define DACRVOLL3 0x0080
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#define DACRVOLR0 0x0084
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#define DACRVOLR1 0x0088
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#define DACRVOLR2 0x008c
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#define DACRVOLR3 0x0090
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#define DACLMT0 0x0094
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#define DACLMT1 0x0098
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#define DACLMT2 0x009c
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#define DACMIXCTRLL 0x00a0
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#define DACMIXCTRLR 0x00a4
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#define DACHPF 0x00a8
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#define I2S_RXCR0 0x010c
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#define I2S_RXCR1 0x0110
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#define I2S_CKR0 0x0114
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#define I2S_CKR1 0x0118
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#define I2S_XFER 0x011c
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#define I2S_CLR 0x0120
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#define VERSION 0x0140
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/* DACDIGEN */
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#define DSM_DACDIGEN_DACEN_L0R1_MASK BIT(0)
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#define DSM_DACDIGEN_DACEN_L0R1_EN BIT(0)
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#define DSM_DACDIGEN_DACEN_L0R1_DIS 0
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#define DSM_DACDIGEN_DAC_GLBEN_MASK BIT(4)
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#define DSM_DACDIGEN_DAC_GLBEN_EN BIT(4)
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#define DSM_DACDIGEN_DAC_GLBEN_DIS 0
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/* DACCLKCTRL */
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#define DSM_DACCLKCTRL_DAC_MODE_ATTENU_MASK BIT(0)
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#define DSM_DACCLKCTRL_DAC_MODE_ATTENU_EN BIT(0)
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#define DSM_DACCLKCTRL_DAC_MODE_ATTENU_DIS 0
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#define DSM_DACCLKCTRL_DAC_SYNC_STATUS_MASK BIT(1)
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#define DSM_DACCLKCTRL_DAC_SYNC_STATUS_DONE 0
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#define DSM_DACCLKCTRL_DAC_SYNC_ENA_MASK BIT(2)
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#define DSM_DACCLKCTRL_DAC_SYNC_ENA_EN BIT(2)
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#define DSM_DACCLKCTRL_DAC_SYNC_ENA_DIS 0
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#define DSM_DACCLKCTRL_CKE_BCLKRX_MASK BIT(3)
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#define DSM_DACCLKCTRL_CKE_BCLKRX_EN BIT(3)
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#define DSM_DACCLKCTRL_CKE_BCLKRX_DIS 0
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#define DSM_DACCLKCTRL_I2SRX_CKE_MASK BIT(4)
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#define DSM_DACCLKCTRL_I2SRX_CKE_EN BIT(4)
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#define DSM_DACCLKCTRL_I2SRX_CKE_DIS 0
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#define DSM_DACCLKCTRL_DAC_CKE_MASK BIT(5)
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#define DSM_DACCLKCTRL_DAC_CKE_EN BIT(5)
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#define DSM_DACCLKCTRL_DAC_CKE_DIS 0
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/* DACINT_DIV */
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#define DSM_DACINT_DIV_INT_DIV_CON_MASK GENMASK(7, 0)
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#define DSM_DACINT_DIV_INT_DIV_CON(x) ((x) - 1)
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/* DACSCLKRXINT_DIV */
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#define DSM_DACSCLKRXINT_DIV_SCKRXDIV_MASK GENMASK(7, 0)
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#define DSM_DACSCLKRXINT_DIV_SCKRXDIV(x) ((x) - 1)
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/* DACPWM_DIV */
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#define DSM_DACPWM_DIV_AUDIO_PWM_DIV_MASK GENMASK(7, 0)
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#define DSM_DACPWM_DIV_AUDIO_PWM_DIV(x) ((x) - 1)
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/* DACPWM_CTRL */
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#define DSM_DACPWM_CTRL_DITH_SEL_MASK GENMASK(2, 0)
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#define DSM_DACPWM_CTRL_DITH_SEL(x) (x)
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#define DSM_DACPWM_CTRL_PWM_EN_MASK BIT(3)
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#define DSM_DACPWM_CTRL_PWM_EN BIT(3)
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#define DSM_DACPWM_CTRL_PWM_DIS 0
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#define DSM_DACPWM_CTRL_PWM_MODE_MASK GENMASK(5, 4)
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#define DSM_DACPWM_CTRL_PWM_MODE_1 (0x2 << 4)
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#define DSM_DACPWM_CTRL_PWM_MODE_0 (0x1 << 4)
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#define DSM_DACPWM_CTRL_PWM_MODE_DAC (0x0 << 4)
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#define DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK BIT(6)
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#define DSM_DACPWM_CTRL_PWM_MODE_CKE_EN BIT(6)
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#define DSM_DACPWM_CTRL_PWM_MODE_CKE_DIS 0
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/* DACCFG1 */
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#define DSM_DACCFG1_DACSRT_MASK GENMASK(4, 2)
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#define DSM_DACCFG1_DACSRT(x) ((x) << 2)
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/* DACMUTE */
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#define DSM_DACMUTE_DACMT_MASK BIT(0)
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#define DSM_DACMUTE_DACUNMT_MASK BIT(1)
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/* DACVOLL0 */
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#define DSM_DACVOLL0_DACLV0_MASK GENMASK(7, 0)
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#define DSM_DACVOLL0_DACLV0(x) (x)
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/* DACVOLR0 */
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#define DSM_DACVOLR0_DACRV0_MASK GENMASK(7, 0)
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#define DSM_DACVOLR0_DACRV0(x) (x)
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/* DACVOGP */
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#define DSM_DACVOGP_VOLGPL0_MASK BIT(0)
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#define DSM_DACVOGP_VOLGPL0_POS BIT(0)
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#define DSM_DACVOGP_VOLGPL0_NEG 0
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#define DSM_DACVOGP_VOLGPR0_MASK BIT(1)
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#define DSM_DACVOGP_VOLGPR0_POS BIT(1)
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#define DSM_DACVOGP_VOLGPR0_NEG 0
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/* DACMIXCTRLL */
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#define DSM_DACMIXCTRLL_MIXMODE_L0_MASK GENMASK(1, 0)
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#define DSM_DACMIXCTRLL_MIXMODE_L0_LR 2
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#define DSM_DACMIXCTRLL_MIXMODE_L0_R 1
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#define DSM_DACMIXCTRLL_MIXMODE_L0_L 0
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/* DACMIXCTRLR */
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#define DSM_DACMIXCTRLR_MIXMODE_R0_MASK GENMASK(1, 0)
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#define DSM_DACMIXCTRLR_MIXMODE_R0_LR 2
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#define DSM_DACMIXCTRLR_MIXMODE_R0_L 1
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#define DSM_DACMIXCTRLR_MIXMODE_R0_R 0
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/* DACHPF */
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#define DSM_DACHPF_HPFEN_L0R0_MASK BIT(0)
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#define DSM_DACHPF_HPFEN_L0R0_EN BIT(0)
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#define DSM_DACHPF_HPFCF_MASK GENMASK(5, 4)
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#define DSM_DACHPF_HPFCF_140HZ (0x3 << 4)
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#define DSM_DACHPF_HPFCF_120HZ (0x2 << 4)
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#define DSM_DACHPF_HPFCF_100HZ (0x1 << 4)
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#define DSM_DACHPF_HPFCF_80HZ (0x0 << 4)
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/* I2S_RXCR0 */
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#define DSM_I2S_RXCR0_VDW_MASK GENMASK(4, 0)
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#define DSM_I2S_RXCR0_VDW(x) ((x) - 1)
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/* I2S_RXCR1 */
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#define DSM_I2S_RXCR1_CEX_MASK BIT(4)
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#define DSM_I2S_RXCR1_CEX_EXCHANGE BIT(4)
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#define DSM_I2S_RXCR1_RCSR_MASK GENMASK(7, 6)
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#define DSM_I2S_RXCR1_RCSR_2CH (0x0 << 6)
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/* I2S_CKR0 */
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#define DSM_I2S_CKR0_RSD_MASK GENMASK(3, 2)
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#define DSM_I2S_CKR0_RSD_64 (0 << 2)
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#define DSM_I2S_CKR0_RSD_128 (1 << 2)
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#define DSM_I2S_CKR0_RSD_256 (2 << 2)
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/* I2S_CKR1 */
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#define DSM_I2S_CKR1_RLP_MASK BIT(1)
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#define DSM_I2S_CKR1_RLP_INVERTED BIT(1)
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#define DSM_I2S_CKR1_RLP_NORMAL 0
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#define DSM_I2S_CKR1_CKP_MASK BIT(2)
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#define DSM_I2S_CKR1_CKP_INVERTED BIT(2)
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#define DSM_I2S_CKR1_CKP_NORMAL 0
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#define DSM_I2S_CKR1_MSS_MASK BIT(3)
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#define DSM_I2S_CKR1_MSS_MASTER 0
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/* I2S_XFER */
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#define DSM_I2S_XFER_RXS_MASK BIT(1)
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#define DSM_I2S_XFER_RXS_START BIT(1)
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#define DSM_I2S_XFER_RXS_STOP 0
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/* I2S_CLR */
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#define DSM_I2S_CLR_RXC_MASK BIT(1)
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#define DSM_I2S_CLR_RXC_CLR BIT(1)
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#endif
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