/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* rk3528_codec.h - Rockchip RK3528 SoC Codec Driver
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*
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __RK3528_CODEC_H__
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#define __RK3528_CODEC_H__
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#define ACODEC_DIG00 0x00 /* REG 0x00 */
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#define ACODEC_DIG01 0x04 /* REG 0x01 */
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#define ACODEC_DIG02 0x08 /* REG 0x02 */
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#define ACODEC_DIG03 0x0c /* REG 0x03 */
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#define ACODEC_DIG04 0x10 /* REG 0x04 */
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#define ACODEC_DIG05 0x14 /* REG 0x05 */
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#define ACODEC_DIG06 0x18 /* REG 0x06 */
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#define ACODEC_DIG07 0x1c /* REG 0x07 */
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#define ACODEC_DIG08 0x20 /* REG 0x08 */
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#define ACODEC_DIG09 0x24 /* REG 0x09 */
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#define ACODEC_DIG0A 0x28 /* REG 0x0a */
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#define ACODEC_DIG0B 0x2c /* REG 0x0b */
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#define ACODEC_DIG0D 0x34 /* REG 0x0d */
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#define ACODEC_DIG0E 0x38 /* REG 0x0e */
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#define ACODEC_DIG10 0x40 /* REG 0x10 */
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#define ACODEC_DIG11 0x44 /* REG 0x11 */
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#define ACODEC_ANA00 0x80 /* REG 0x20 */
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#define ACODEC_ANA01 0x84 /* REG 0x21 */
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#define ACODEC_ANA02 0x88 /* REG 0x22 */
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#define ACODEC_ANA08 0xa0 /* REG 0x28 */
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#define ACODEC_ANA09 0xa4 /* REG 0x29 */
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#define ACODEC_ANA0A 0xa8 /* REG 0x2a */
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#define ACODEC_ANA0B 0xac /* REG 0x2b */
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#define ACODEC_ANA0C 0xb0 /* REG 0x2c */
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#define ACODEC_ANA0D 0xb4 /* REG 0x2d */
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#define ACODEC_ANA0E 0xb8 /* REG 0x2e */
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#define ACODEC_ANA0F 0xbc /* REG 0x2f */
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#define ACODEC_REG_MAX ACODEC_ANA0F
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/* ACODEC_DIG00 */
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#define ACODEC_DAC_RST_MASK (0x1 << 4)
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#define ACODEC_DAC_RST_P (0x1 << 4)
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#define ACODEC_DAC_RST_N (0x0 << 4)
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#define ACODEC_REG_BIST_EN (0x1 << 1)
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#define ACODEC_SYS_RST_MASK (0x1 << 0)
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#define ACODEC_SYS_RST_P (0x1 << 0)
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#define ACODEC_SYS_RST_N (0x0 << 0)
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/* ACODEC_DIG01 */
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#define ACODEC_DAC_I2S_WL_SHIFT 4
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#define ACODEC_DAC_I2S_WL_MASK (0x3 << ACODEC_DAC_I2S_WL_SHIFT)
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#define ACODEC_DAC_I2S_32B (0x3 << ACODEC_DAC_I2S_WL_SHIFT)
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#define ACODEC_DAC_I2S_24B (0x2 << ACODEC_DAC_I2S_WL_SHIFT)
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#define ACODEC_DAC_I2S_20B (0x1 << ACODEC_DAC_I2S_WL_SHIFT)
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#define ACODEC_DAC_I2S_16B (0x0 << ACODEC_DAC_I2S_WL_SHIFT)
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#define ACODEC_DAC_I2S_FMT_SHIFT 2
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#define ACODEC_DAC_I2S_FMT_MASK (0x3 << ACODEC_DAC_I2S_FMT_SHIFT)
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#define ACODEC_DAC_I2S_I2S (0x2 << ACODEC_DAC_I2S_FMT_SHIFT)
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#define ACODEC_DAC_I2S_LJM (0x1 << ACODEC_DAC_I2S_FMT_SHIFT)
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/* ACODEC_DIG02 */
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#define ACODEC_DAC_I2S_LRP_MASK (0x1 << 7)
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#define ACODEC_DAC_I2S_LRP_REVSL (0x1 << 7)
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#define ACODEC_DAC_I2S_LRP_NORMAL (0x0 << 7)
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#define ACODEC_DAC_I2S_LR_SWAP (0x1 << 6)
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#define ACODEC_DAC_I2S_MST_FUNC_MASK (0x1 << 5)
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#define ACODEC_DAC_I2S_MST_FUNC_MASTER (0x1 << 5)
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#define ACODEC_DAC_I2S_MST_FUNC_SLAVE (0x0 << 5)
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#define ACODEC_DAC_I2S_MST_IO_MASK (0x1 << 4)
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#define ACODEC_DAC_I2S_MST_IO_MASTER (0x1 << 4)
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#define ACODEC_DAC_I2S_MST_IO_SLAVE (0x0 << 4)
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#define ACODEC_DAC_I2S_RST_MASK (0x1 << 0)
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#define ACODEC_DAC_I2S_RST_P (0x1 << 0)
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#define ACODEC_DAC_I2S_RST_N (0x0 << 0)
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/* ACODEC_DIG03 */
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#define ACODEC_DAC_MUTE_EN (0x1 << 7)
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#define ACODEC_DAC_MUTE_SR_SHIFT 4
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#define ACODEC_DAC_MUTE_SR_MASK (0x7 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_96K (0x7 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_88K2 (0x6 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_48K (0x5 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_44K1 (0x4 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_32K (0x3 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_24K (0x2 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_16K (0x1 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DAC_MUTE_SR_8K (0x0 << ACODEC_DAC_MUTE_SR_SHIFT)
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#define ACODEC_DA_EN (0x1 << 3)
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#define ACODEC_DITHER_EN (0x1 << 2)
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#define ACODEC_DITHER_LEVEL (0x1 << 1)
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#define ACODEC_DITHER_SIGN (0x1 << 0)
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/* ACODEC_DIG04 */
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#define ACODEC_DAC_DEEMP_SEL_MASK 0x3
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#define ACODEC_DAC_DEEMP_48K 0x3
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#define ACODEC_DAC_DEEMP_44K1 0x2
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#define ACODEC_DAC_DEEMP_32K 0x1
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#define ACODEC_DAC_DEEMP_DIS 0x0
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/* ACODEC_DIG05 */
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#define ACODEC_DAC_R_BIST_SEL_SHIFT 6
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#define ACODEC_DAC_R_BIST_SEL_MASK (0x3 << ACODEC_DAC_R_BIST_SEL_SHIFT)
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#define ACODEC_DAC_R_BIST_SEL_L (0x2 << ACODEC_DAC_R_BIST_SEL_SHIFT)
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#define ACODEC_DAC_R_BIST_SEL_SINE (0x1 << ACODEC_DAC_R_BIST_SEL_SHIFT)
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#define ACODEC_DAC_R_BIST_SEL_R (0x0 << ACODEC_DAC_R_BIST_SEL_SHIFT)
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#define ACODEC_DAC_R_MUTE (0x1 << 4)
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#define ACODEC_DAC_L_BIST_SEL_SHIFT 2
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#define ACODEC_DAC_L_BIST_SEL_MASK (0x3 << ACODEC_DAC_L_BIST_SEL_SHIFT)
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#define ACODEC_DAC_L_BIST_SEL_R (0x2 << ACODEC_DAC_L_BIST_SEL_SHIFT)
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#define ACODEC_DAC_L_BIST_SEL_SINE (0x1 << ACODEC_DAC_L_BIST_SEL_SHIFT)
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#define ACODEC_DAC_L_BIST_SEL_L (0x0 << ACODEC_DAC_L_BIST_SEL_SHIFT)
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#define ACODEC_DAC_J_MUTE (0x1 << 0)
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/* ACODEC_DIG06 */
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#define ACODEC_DAC_DIG_GAIN_SHIT 0
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#define ACODEC_DAC_DIG_GAIN_MASK (0xff << ACODEC_DAC_DIG_GAIN_SHIT)
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/* 0.5dB every step , 1: -121dB, 255: 6dB */
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#define ACODEC_DAC_DIG_GAIN(x) ((x) & ACODEC_DAC_DIG_GAIN_MASK)
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#define ACODEC_DAC_DIG_0DB 0xe1
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/* ACODEC_ANA00 */
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#define ACODEC_IBIAS_DAC_MASK (0x1 << 1)
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#define ACODEC_IBIAS_DAC_EN (0x1 << 1)
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#define ACODEC_IBIAS_DAC_DIS (0x0 << 1)
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#define ACODEC_VREF_MASK (0x1 << 0)
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#define ACODEC_VREF_EN (0x1 << 0)
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#define ACODEC_VREF_DIS (0x0 << 0)
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/* ACODEC_ANA01 */
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#define ACODEC_VREF_SEL_SHIFT 0
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/* Bit 0 is I0, bit 1 is 2 * I0 ... bit 7 is 128 * I0 */
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#define ACODEC_VREF_SEL_MASK (0xff << ACODEC_VREF_SEL_SHIFT)
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#define ACODEC_VREF_SEL(x) ((x) & ACODEC_VREF_SEL_MASK)
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/* ACODEC_ANA02 */
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#define ACODEC_IBIAS_DAC_SEL_SHIFT 0
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/* Ibias_DAC = I0 * (BIT[3]*8+BIT[2]*4+BIT[1]*2+BIT[0]+1) */
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#define ACODEC_IBIAS_DAC_SEL (0xf << ACODEC_IBIAS_DAC_SEL_SHIFT)
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/* ACODEC_ANA08 */
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#define ACODEC_DAC_L_POP_CTRL_SHIFT 5
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#define ACODEC_DAC_L_POP_CTRL_MASK (0x3 << ACODEC_DAC_L_POP_CTRL_SHIFT)
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#define ACODEC_DAC_L_POP_CTRL_ON (0x1 << ACODEC_DAC_L_POP_CTRL_SHIFT)
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#define ACODEC_DAC_L_POP_CTRL_OFF (0x0 << ACODEC_DAC_L_POP_CTRL_SHIFT)
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#define ACODEC_DAC_L_INIT_MASK (0x1 << 4)
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#define ACODEC_DAC_L_WORK (0x1 << 4)
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#define ACODEC_DAC_L_INIT (0x0 << 4)
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#define ACODEC_DAC_L_VREF_MASK (0x1 << 3)
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#define ACODEC_DAC_L_VREF_EN (0x1 << 3)
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#define ACODEC_DAC_L_VREF_DIS (0x0 << 3)
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#define ACODEC_DAC_L_BUF_MASK (0x1 << 2)
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#define ACODEC_DAC_L_BUF_EN (0x1 << 2)
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#define ACODEC_DAC_L_BUF_DIS (0x0 << 2)
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#define ACODEC_DAC_L_CLK_MASK (0x1 << 1)
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#define ACODEC_DAC_L_CLK_EN (0x1 << 1)
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#define ACODEC_DAC_L_CLK_DIS (0x0 << 1)
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#define ACODEC_DAC_L_MASK (0x1 << 0)
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#define ACODEC_DAC_L_EN (0x1 << 0)
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#define ACODEC_DAC_L_DIS (0x0 << 0)
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/* ACODEC_ANA09 */
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#define ACODEC_LINEOUT_L_MUTE_MASK (0x1 << 5)
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#define ACODEC_LINEOUT_L_WORK (0x1 << 5)
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#define ACODEC_LINEOUT_L_MUTE (0x0 << 5)
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#define ACODEC_LINEOUT_L_INIT_MASK (0x1 << 4)
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#define ACODEC_LINEOUT_L_INIT_WORK (0x1 << 4)
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#define ACODEC_LINEOUT_L_INIT (0x0 << 4)
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#define ACODEC_LINEOUT_L_MASK (0x1 << 0)
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#define ACODEC_LINEOUT_L_EN (0x1 << 0)
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#define ACODEC_LINEOUT_L_DIS (0x0 << 0)
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/* ACODEC_ANA0A */
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#define ACODEC_LINEOUT_L_SEL_SHIFT 0
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#define ACODEC_LINEOUT_L_SEL_MASK (0xf << ACODEC_LINEOUT_L_SEL_SHIFT)
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/* ACODEC_ANA0B */
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#define ACODEC_LINEOUT_L_GAIN_SHIFT 0
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/* 1.5dB every step. 0: -39dB, 0x1f: 0dB */
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#define ACODEC_LINEOUT_L_GAIN_MASK (0x1f << ACODEC_LINEOUT_L_GAIN_SHIFT)
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/* ACODEC_ANA0C */
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#define ACODEC_DAC_R_POP_CTRL_SHIFT 5
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#define ACODEC_DAC_R_POP_CTRL_MASK (0x3 << ACODEC_DAC_R_POP_CTRL_SHIFT)
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#define ACODEC_DAC_R_POP_CTRL_ON (0x1 << ACODEC_DAC_R_POP_CTRL_SHIFT)
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#define ACODEC_DAC_R_POP_CTRL_OFF (0x0 << ACODEC_DAC_R_POP_CTRL_SHIFT)
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#define ACODEC_DAC_R_INIT_MASK (0x1 << 4)
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#define ACODEC_DAC_R_WORK (0x1 << 4)
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#define ACODEC_DAC_R_INIT (0x0 << 4)
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#define ACODEC_DAC_R_VREF_MASK (0x1 << 3)
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#define ACODEC_DAC_R_VREF_EN (0x1 << 3)
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#define ACODEC_DAC_R_VREF_DIS (0x0 << 3)
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#define ACODEC_DAC_R_BUF_MASK (0x1 << 2)
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#define ACODEC_DAC_R_BUF_EN (0x1 << 2)
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#define ACODEC_DAC_R_BUF_DIS (0x0 << 2)
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#define ACODEC_DAC_R_CLK_MASK (0x1 << 1)
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#define ACODEC_DAC_R_CLK_EN (0x1 << 1)
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#define ACODEC_DAC_R_CLK_DIS (0x0 << 1)
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#define ACODEC_DAC_R_MASK (0x1 << 0)
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#define ACODEC_DAC_R_EN (0x1 << 0)
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#define ACODEC_DAC_R_DIS (0x0 << 0)
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/* ACODEC_ANA0D */
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#define ACODEC_LINEOUT_R_MUTE_MASK (0x1 << 5)
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#define ACODEC_LINEOUT_R_WORK (0x1 << 5)
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#define ACODEC_LINEOUT_R_MUTE (0x0 << 5)
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#define ACODEC_LINEOUT_R_INIT_MASK (0x1 << 4)
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#define ACODEC_LINEOUT_R_INIT_WORK (0x1 << 4)
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#define ACODEC_LINEOUT_R_INIT (0x0 << 4)
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#define ACODEC_LINEOUT_R_MASK (0x1 << 0)
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#define ACODEC_LINEOUT_R_EN (0x1 << 0)
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#define ACODEC_LINEOUT_R_DIS (0x0 << 0)
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/* ACODEC_ANA0E */
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#define ACODEC_LINEOUT_R_SEL_SHIFT 0
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#define ACODEC_LINEOUT_R_SEL_MASK (0xf << ACODEC_LINEOUT_L_SEL_SHIFT)
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/* ACODEC_ANA0F */
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#define ACODEC_LINEOUT_R_GAIN_SHIFT 0
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/* 1.5dB every step. 0: -39dB, 0x1f: 0dB */
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#define ACODEC_LINEOUT_R_GAIN_MASK (0x1f << ACODEC_LINEOUT_L_GAIN_SHIFT)
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#define ACODEC_DAC_LINEOUT_GAIN_MAX 0x1e
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#define ACODEC_DAC_LINEOUT_GAIN_MIN 0
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#define ACODEC_HIFI 0x0
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#define ACODEC_DAC_LINEOUT_GAIN_0DB 0x1a
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#endif /* __RK3528_CODEC_H__ */
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