/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
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#ifndef __ABI_MACH_T194_RESET_H
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#define __ABI_MACH_T194_RESET_H
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#define TEGRA194_RESET_ACTMON 1
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#define TEGRA194_RESET_ADSP_ALL 2
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#define TEGRA194_RESET_AFI 3
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#define TEGRA194_RESET_CAN1 4
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#define TEGRA194_RESET_CAN2 5
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#define TEGRA194_RESET_DLA0 6
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#define TEGRA194_RESET_DLA1 7
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#define TEGRA194_RESET_DPAUX 8
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#define TEGRA194_RESET_DPAUX1 9
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#define TEGRA194_RESET_DPAUX2 10
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#define TEGRA194_RESET_DPAUX3 11
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#define TEGRA194_RESET_EQOS 17
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#define TEGRA194_RESET_GPCDMA 18
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#define TEGRA194_RESET_GPU 19
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#define TEGRA194_RESET_HDA 20
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#define TEGRA194_RESET_HDA2CODEC_2X 21
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#define TEGRA194_RESET_HDA2HDMICODEC 22
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#define TEGRA194_RESET_HOST1X 23
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#define TEGRA194_RESET_I2C1 24
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#define TEGRA194_RESET_I2C10 25
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#define TEGRA194_RESET_RSVD_26 26
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#define TEGRA194_RESET_RSVD_27 27
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#define TEGRA194_RESET_RSVD_28 28
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#define TEGRA194_RESET_I2C2 29
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#define TEGRA194_RESET_I2C3 30
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#define TEGRA194_RESET_I2C4 31
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#define TEGRA194_RESET_I2C6 32
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#define TEGRA194_RESET_I2C7 33
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#define TEGRA194_RESET_I2C8 34
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#define TEGRA194_RESET_I2C9 35
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#define TEGRA194_RESET_ISP 36
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#define TEGRA194_RESET_MIPI_CAL 37
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#define TEGRA194_RESET_MPHY_CLK_CTL 38
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#define TEGRA194_RESET_MPHY_L0_RX 39
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#define TEGRA194_RESET_MPHY_L0_TX 40
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#define TEGRA194_RESET_MPHY_L1_RX 41
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#define TEGRA194_RESET_MPHY_L1_TX 42
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#define TEGRA194_RESET_NVCSI 43
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#define TEGRA194_RESET_NVDEC 44
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#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45
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#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46
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#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47
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#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48
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#define TEGRA194_RESET_NVDISPLAY0_MISC 49
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#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50
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#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51
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#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52
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#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53
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#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54
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#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55
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#define TEGRA194_RESET_RSVD_56 56
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#define TEGRA194_RESET_RSVD_57 57
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#define TEGRA194_RESET_RSVD_58 58
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#define TEGRA194_RESET_NVENC 59
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#define TEGRA194_RESET_NVENC1 60
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#define TEGRA194_RESET_NVJPG 61
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#define TEGRA194_RESET_PCIE 62
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#define TEGRA194_RESET_PCIEXCLK 63
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#define TEGRA194_RESET_RSVD_64 64
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#define TEGRA194_RESET_RSVD_65 65
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#define TEGRA194_RESET_PVA0_ALL 66
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#define TEGRA194_RESET_PVA1_ALL 67
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#define TEGRA194_RESET_PWM1 68
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#define TEGRA194_RESET_PWM2 69
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#define TEGRA194_RESET_PWM3 70
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#define TEGRA194_RESET_PWM4 71
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#define TEGRA194_RESET_PWM5 72
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#define TEGRA194_RESET_PWM6 73
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#define TEGRA194_RESET_PWM7 74
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#define TEGRA194_RESET_PWM8 75
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#define TEGRA194_RESET_QSPI0 76
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#define TEGRA194_RESET_QSPI1 77
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#define TEGRA194_RESET_SATA 78
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#define TEGRA194_RESET_SATACOLD 79
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#define TEGRA194_RESET_SCE_ALL 80
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#define TEGRA194_RESET_RCE_ALL 81
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#define TEGRA194_RESET_SDMMC1 82
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#define TEGRA194_RESET_RSVD_83 83
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#define TEGRA194_RESET_SDMMC3 84
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#define TEGRA194_RESET_SDMMC4 85
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#define TEGRA194_RESET_SE 86
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#define TEGRA194_RESET_SOR0 87
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#define TEGRA194_RESET_SOR1 88
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#define TEGRA194_RESET_SOR2 89
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#define TEGRA194_RESET_SOR3 90
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#define TEGRA194_RESET_SPI1 91
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#define TEGRA194_RESET_SPI2 92
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#define TEGRA194_RESET_SPI3 93
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#define TEGRA194_RESET_SPI4 94
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#define TEGRA194_RESET_TACH 95
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#define TEGRA194_RESET_RSVD_96 96
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#define TEGRA194_RESET_TSCTNVI 97
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#define TEGRA194_RESET_TSEC 98
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#define TEGRA194_RESET_TSECB 99
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#define TEGRA194_RESET_UARTA 100
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#define TEGRA194_RESET_UARTB 101
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#define TEGRA194_RESET_UARTC 102
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#define TEGRA194_RESET_UARTD 103
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#define TEGRA194_RESET_UARTE 104
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#define TEGRA194_RESET_UARTF 105
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#define TEGRA194_RESET_UARTG 106
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#define TEGRA194_RESET_UARTH 107
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#define TEGRA194_RESET_UFSHC 108
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#define TEGRA194_RESET_UFSHC_AXI_M 109
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#define TEGRA194_RESET_UFSHC_LP_SEQ 110
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#define TEGRA194_RESET_RSVD_111 111
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#define TEGRA194_RESET_VI 112
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#define TEGRA194_RESET_VIC 113
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#define TEGRA194_RESET_XUSB_PADCTL 114
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#define TEGRA194_RESET_NVDEC1 115
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#define TEGRA194_RESET_PEX0_CORE_0 116
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#define TEGRA194_RESET_PEX0_CORE_1 117
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#define TEGRA194_RESET_PEX0_CORE_2 118
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#define TEGRA194_RESET_PEX0_CORE_3 119
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#define TEGRA194_RESET_PEX0_CORE_4 120
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#define TEGRA194_RESET_PEX0_CORE_0_APB 121
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#define TEGRA194_RESET_PEX0_CORE_1_APB 122
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#define TEGRA194_RESET_PEX0_CORE_2_APB 123
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#define TEGRA194_RESET_PEX0_CORE_3_APB 124
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#define TEGRA194_RESET_PEX0_CORE_4_APB 125
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#define TEGRA194_RESET_PEX0_COMMON_APB 126
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#define TEGRA194_RESET_PEX1_CORE_5 129
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#define TEGRA194_RESET_PEX1_CORE_5_APB 130
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#define TEGRA194_RESET_CVNAS 131
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#define TEGRA194_RESET_CVNAS_FCM 132
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#define TEGRA194_RESET_DMIC5 144
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#define TEGRA194_RESET_APE 145
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#define TEGRA194_RESET_PEX_USB_UPHY 146
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#define TEGRA194_RESET_PEX_USB_UPHY_L0 147
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#define TEGRA194_RESET_PEX_USB_UPHY_L1 148
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#define TEGRA194_RESET_PEX_USB_UPHY_L2 149
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#define TEGRA194_RESET_PEX_USB_UPHY_L3 150
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#define TEGRA194_RESET_PEX_USB_UPHY_L4 151
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#define TEGRA194_RESET_PEX_USB_UPHY_L5 152
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#define TEGRA194_RESET_PEX_USB_UPHY_L6 153
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#define TEGRA194_RESET_PEX_USB_UPHY_L7 154
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#define TEGRA194_RESET_PEX_USB_UPHY_L8 155
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#define TEGRA194_RESET_PEX_USB_UPHY_L9 156
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#define TEGRA194_RESET_PEX_USB_UPHY_L10 157
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#define TEGRA194_RESET_PEX_USB_UPHY_L11 158
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162
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#endif
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