/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
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#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
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/* INFRACFG resets */
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#define MT2701_INFRA_EMI_REG_RST 0
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#define MT2701_INFRA_DRAMC0_A0_RST 1
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#define MT2701_INFRA_FHCTL_RST 2
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#define MT2701_INFRA_APCIRQ_EINT_RST 3
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#define MT2701_INFRA_APXGPT_RST 4
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#define MT2701_INFRA_SCPSYS_RST 5
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#define MT2701_INFRA_KP_RST 6
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#define MT2701_INFRA_PMIC_WRAP_RST 7
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#define MT2701_INFRA_MIPI_RST 8
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#define MT2701_INFRA_IRRX_RST 9
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#define MT2701_INFRA_CEC_RST 10
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#define MT2701_INFRA_EMI_RST 32
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#define MT2701_INFRA_DRAMC0_RST 34
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#define MT2701_INFRA_TRNG_RST 37
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#define MT2701_INFRA_SYSIRQ_RST 38
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/* PERICFG resets */
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#define MT2701_PERI_UART0_SW_RST 0
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#define MT2701_PERI_UART1_SW_RST 1
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#define MT2701_PERI_UART2_SW_RST 2
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#define MT2701_PERI_UART3_SW_RST 3
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#define MT2701_PERI_GCPU_SW_RST 5
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#define MT2701_PERI_BTIF_SW_RST 6
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#define MT2701_PERI_PWM_SW_RST 8
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#define MT2701_PERI_AUXADC_SW_RST 10
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#define MT2701_PERI_DMA_SW_RST 11
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#define MT2701_PERI_NFI_SW_RST 14
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#define MT2701_PERI_NLI_SW_RST 15
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#define MT2701_PERI_THERM_SW_RST 16
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#define MT2701_PERI_MSDC2_SW_RST 17
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#define MT2701_PERI_MSDC0_SW_RST 19
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#define MT2701_PERI_MSDC1_SW_RST 20
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#define MT2701_PERI_I2C0_SW_RST 22
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#define MT2701_PERI_I2C1_SW_RST 23
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#define MT2701_PERI_I2C2_SW_RST 24
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#define MT2701_PERI_I2C3_SW_RST 25
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#define MT2701_PERI_USB_SW_RST 28
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#define MT2701_PERI_ETH_SW_RST 29
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#define MT2701_PERI_SPI0_SW_RST 33
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/* TOPRGU resets */
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#define MT2701_TOPRGU_INFRA_RST 0
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#define MT2701_TOPRGU_MM_RST 1
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#define MT2701_TOPRGU_MFG_RST 2
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#define MT2701_TOPRGU_ETHDMA_RST 3
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#define MT2701_TOPRGU_VDEC_RST 4
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#define MT2701_TOPRGU_VENC_IMG_RST 5
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#define MT2701_TOPRGU_DDRPHY_RST 6
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#define MT2701_TOPRGU_MD_RST 7
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#define MT2701_TOPRGU_INFRA_AO_RST 8
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#define MT2701_TOPRGU_CONN_RST 9
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#define MT2701_TOPRGU_APMIXED_RST 10
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#define MT2701_TOPRGU_HIFSYS_RST 11
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#define MT2701_TOPRGU_CONN_MCU_RST 12
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#define MT2701_TOPRGU_BDP_DISP_RST 13
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/* HIFSYS resets */
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#define MT2701_HIFSYS_UHOST0_RST 3
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#define MT2701_HIFSYS_UHOST1_RST 4
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#define MT2701_HIFSYS_UPHY0_RST 21
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#define MT2701_HIFSYS_UPHY1_RST 22
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#define MT2701_HIFSYS_PCIE0_RST 24
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#define MT2701_HIFSYS_PCIE1_RST 25
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#define MT2701_HIFSYS_PCIE2_RST 26
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/* ETHSYS resets */
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#define MT2701_ETHSYS_SYS_RST 0
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#define MT2701_ETHSYS_MCM_RST 2
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#define MT2701_ETHSYS_FE_RST 6
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#define MT2701_ETHSYS_GMAC_RST 23
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#define MT2701_ETHSYS_PPE_RST 31
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/* G3DSYS resets */
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#define MT2701_G3DSYS_CORE_RST 0
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
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