/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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* Author: Xingyu Chen <xingyu.chen@amlogic.com>
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*
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
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/* RESET0 */
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/* 0 */
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#define RESET_AM2AXI_VAD 1
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/* 2-3 */
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#define RESET_PSRAM 4
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#define RESET_PAD_CTRL 5
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/* 6 */
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#define RESET_TEMP_SENSOR 7
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#define RESET_AM2AXI_DEV 8
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/* 9 */
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#define RESET_SPICC_A 10
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#define RESET_MSR_CLK 11
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#define RESET_AUDIO 12
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#define RESET_ANALOG_CTRL 13
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#define RESET_SAR_ADC 14
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#define RESET_AUDIO_VAD 15
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#define RESET_CEC 16
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#define RESET_PWM_EF 17
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#define RESET_PWM_CD 18
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#define RESET_PWM_AB 19
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/* 20 */
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#define RESET_IR_CTRL 21
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#define RESET_I2C_S_A 22
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/* 23 */
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#define RESET_I2C_M_D 24
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#define RESET_I2C_M_C 25
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#define RESET_I2C_M_B 26
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#define RESET_I2C_M_A 27
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#define RESET_I2C_PROD_AHB 28
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#define RESET_I2C_PROD 29
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/* 30-31 */
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/* RESET1 */
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#define RESET_ACODEC 32
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#define RESET_DMA 33
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#define RESET_SD_EMMC_A 34
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/* 35 */
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#define RESET_USBCTRL 36
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/* 37 */
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#define RESET_USBPHY 38
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/* 39-41 */
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#define RESET_RSA 42
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#define RESET_DMC 43
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/* 44 */
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#define RESET_IRQ_CTRL 45
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/* 46 */
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#define RESET_NIC_VAD 47
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#define RESET_NIC_AXI 48
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#define RESET_RAMA 49
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#define RESET_RAMB 50
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/* 51-52 */
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#define RESET_ROM 53
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#define RESET_SPIFC 54
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#define RESET_GIC 55
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#define RESET_UART_C 56
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#define RESET_UART_B 57
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#define RESET_UART_A 58
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#define RESET_OSC_RING 59
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/* 60-63 */
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/* RESET2 */
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/* 64-95 */
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#endif
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