// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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//
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// Device Tree binding constants for Actions Semi S900 Reset Management Unit
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//
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// Copyright (c) 2018 Linaro Ltd.
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#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
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#define __DT_BINDINGS_ACTIONS_S900_RESET_H
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#define RESET_CHIPID 0
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#define RESET_CPU_SCNT 1
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#define RESET_SRAMI 2
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#define RESET_DDR_CTL_PHY 3
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#define RESET_DMAC 4
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#define RESET_GPIO 5
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#define RESET_BISP_AXI 6
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#define RESET_CSI0 7
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#define RESET_CSI1 8
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#define RESET_DE 9
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#define RESET_DSI 10
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#define RESET_GPU3D_PA 11
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#define RESET_GPU3D_PB 12
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#define RESET_HDE 13
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#define RESET_I2C0 14
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#define RESET_I2C1 15
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#define RESET_I2C2 16
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#define RESET_I2C3 17
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#define RESET_I2C4 18
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#define RESET_I2C5 19
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#define RESET_IMX 20
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#define RESET_NANDC0 21
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#define RESET_NANDC1 22
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#define RESET_SD0 23
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#define RESET_SD1 24
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#define RESET_SD2 25
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#define RESET_SD3 26
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#define RESET_SPI0 27
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#define RESET_SPI1 28
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#define RESET_SPI2 29
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#define RESET_SPI3 30
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#define RESET_UART0 31
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#define RESET_UART1 32
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#define RESET_UART2 33
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#define RESET_UART3 34
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#define RESET_UART4 35
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#define RESET_UART5 36
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#define RESET_UART6 37
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#define RESET_HDMI 38
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#define RESET_LVDS 39
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#define RESET_EDP 40
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#define RESET_USB2HUB 41
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#define RESET_USB2HSIC 42
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#define RESET_USB3 43
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#define RESET_PCM1 44
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#define RESET_AUDIO 45
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#define RESET_PCM0 46
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#define RESET_SE 47
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#define RESET_GIC 48
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#define RESET_DDR_CTL_PHY_AXI 49
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#define RESET_CMU_DDR 50
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#define RESET_DMM 51
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#define RESET_HDCP2TX 52
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#define RESET_ETHERNET 53
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#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */
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