/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _DT_BINDINGS_PHY_SNPS_PCIE3
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#define _DT_BINDINGS_PHY_SNPS_PCIE3
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/*
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* pcie30_phy_mode[2:0]
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* bit2: aggregation
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* bit1: bifurcation for port 1
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* bit0: bifurcation for port 0
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*/
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#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
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#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
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#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
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#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
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#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
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#endif /* _DT_BINDINGS_PHY_SNPS_PCIE3 */
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