/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
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#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
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#define DDR3_DS_34ohm (34)
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#define DDR3_DS_40ohm (40)
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#define DDR3_ODT_DIS (0)
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#define DDR3_ODT_40ohm (40)
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#define DDR3_ODT_60ohm (60)
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#define DDR3_ODT_120ohm (120)
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#define LP2_DS_34ohm (34)
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#define LP2_DS_40ohm (40)
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#define LP2_DS_48ohm (48)
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#define LP2_DS_60ohm (60)
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#define LP2_DS_68_6ohm (68) /* optional */
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#define LP2_DS_80ohm (80)
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#define LP2_DS_120ohm (120) /* optional */
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#define LP3_DS_34ohm (34)
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#define LP3_DS_40ohm (40)
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#define LP3_DS_48ohm (48)
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#define LP3_DS_60ohm (60)
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#define LP3_DS_80ohm (80)
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#define LP3_DS_34D_40U (3440)
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#define LP3_DS_40D_48U (4048)
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#define LP3_DS_34D_48U (3448)
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#define LP3_ODT_DIS (0)
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#define LP3_ODT_60ohm (60)
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#define LP3_ODT_120ohm (120)
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#define LP3_ODT_240ohm (240)
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#define LP4_PDDS_40ohm (40)
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#define LP4_PDDS_48ohm (48)
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#define LP4_PDDS_60ohm (60)
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#define LP4_PDDS_80ohm (80)
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#define LP4_PDDS_120ohm (120)
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#define LP4_PDDS_240ohm (240)
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#define LP4_DQ_ODT_40ohm (40)
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#define LP4_DQ_ODT_48ohm (48)
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#define LP4_DQ_ODT_60ohm (60)
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#define LP4_DQ_ODT_80ohm (80)
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#define LP4_DQ_ODT_120ohm (120)
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#define LP4_DQ_ODT_240ohm (240)
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#define LP4_DQ_ODT_DIS (0)
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#define LP4_CA_ODT_40ohm (40)
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#define LP4_CA_ODT_48ohm (48)
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#define LP4_CA_ODT_60ohm (60)
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#define LP4_CA_ODT_80ohm (80)
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#define LP4_CA_ODT_120ohm (120)
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#define LP4_CA_ODT_240ohm (240)
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#define LP4_CA_ODT_DIS (0)
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#define DDR4_DS_34ohm (34)
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#define DDR4_DS_48ohm (48)
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#define DDR4_RTT_NOM_DIS (0)
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#define DDR4_RTT_NOM_60ohm (60)
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#define DDR4_RTT_NOM_120ohm (120)
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#define DDR4_RTT_NOM_40ohm (40)
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#define DDR4_RTT_NOM_240ohm (240)
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#define DDR4_RTT_NOM_48ohm (48)
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#define DDR4_RTT_NOM_80ohm (80)
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#define DDR4_RTT_NOM_34ohm (34)
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#define PHY_DDR3_RON_RTT_DISABLE (0)
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#define PHY_DDR3_RON_RTT_451ohm (1)
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#define PHY_DDR3_RON_RTT_225ohm (2)
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#define PHY_DDR3_RON_RTT_150ohm (3)
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#define PHY_DDR3_RON_RTT_112ohm (4)
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#define PHY_DDR3_RON_RTT_90ohm (5)
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#define PHY_DDR3_RON_RTT_75ohm (6)
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#define PHY_DDR3_RON_RTT_64ohm (7)
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#define PHY_DDR3_RON_RTT_56ohm (16)
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#define PHY_DDR3_RON_RTT_50ohm (17)
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#define PHY_DDR3_RON_RTT_45ohm (18)
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#define PHY_DDR3_RON_RTT_41ohm (19)
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#define PHY_DDR3_RON_RTT_37ohm (20)
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#define PHY_DDR3_RON_RTT_34ohm (21)
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#define PHY_DDR3_RON_RTT_33ohm (22)
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#define PHY_DDR3_RON_RTT_30ohm (23)
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#define PHY_DDR3_RON_RTT_28ohm (24)
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#define PHY_DDR3_RON_RTT_26ohm (25)
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#define PHY_DDR3_RON_RTT_25ohm (26)
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#define PHY_DDR3_RON_RTT_23ohm (27)
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#define PHY_DDR3_RON_RTT_22ohm (28)
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#define PHY_DDR3_RON_RTT_21ohm (29)
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#define PHY_DDR3_RON_RTT_20ohm (30)
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#define PHY_DDR3_RON_RTT_19ohm (31)
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#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
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#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
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#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
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#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
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#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
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#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
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#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
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#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
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#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
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#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
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#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
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#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
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#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
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#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
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#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
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#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
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#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
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#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
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#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
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#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
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#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
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#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
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#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
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#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
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#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
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