/* SPDX-License-Identifier: GPL-2.0 */
|
/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
|
|
#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
|
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
|
|
/** @brief output of gate CLK_ENB_FUSE */
|
#define TEGRA234_CLK_FUSE 40
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
|
#define TEGRA234_CLK_SDMMC4 123
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
|
#define TEGRA234_CLK_UARTA 155
|
|
#endif
|
