/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*
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* Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
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*
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*/
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#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
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#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
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#define CLK_CPU 11
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#define CLK_BUS_DMA 14
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#define CLK_BUS_MMC0 15
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#define CLK_BUS_MMC1 16
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#define CLK_BUS_DRAM 17
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#define CLK_BUS_SPI0 18
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#define CLK_BUS_SPI1 19
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#define CLK_BUS_OTG 20
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#define CLK_BUS_VE 21
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#define CLK_BUS_LCD 22
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#define CLK_BUS_DEINTERLACE 23
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#define CLK_BUS_CSI 24
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#define CLK_BUS_TVD 25
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#define CLK_BUS_TVE 26
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#define CLK_BUS_DE_BE 27
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#define CLK_BUS_DE_FE 28
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#define CLK_BUS_CODEC 29
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#define CLK_BUS_SPDIF 30
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#define CLK_BUS_IR 31
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#define CLK_BUS_RSB 32
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#define CLK_BUS_I2S0 33
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#define CLK_BUS_I2C0 34
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#define CLK_BUS_I2C1 35
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#define CLK_BUS_I2C2 36
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#define CLK_BUS_PIO 37
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#define CLK_BUS_UART0 38
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#define CLK_BUS_UART1 39
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#define CLK_BUS_UART2 40
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#define CLK_MMC0 41
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#define CLK_MMC0_SAMPLE 42
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#define CLK_MMC0_OUTPUT 43
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#define CLK_MMC1 44
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#define CLK_MMC1_SAMPLE 45
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#define CLK_MMC1_OUTPUT 46
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#define CLK_I2S 47
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#define CLK_SPDIF 48
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#define CLK_USB_PHY0 49
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#define CLK_DRAM_VE 50
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#define CLK_DRAM_CSI 51
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#define CLK_DRAM_DEINTERLACE 52
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#define CLK_DRAM_TVD 53
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#define CLK_DRAM_DE_FE 54
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#define CLK_DRAM_DE_BE 55
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#define CLK_DE_BE 56
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#define CLK_DE_FE 57
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#define CLK_TCON 58
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#define CLK_DEINTERLACE 59
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#define CLK_TVE2_CLK 60
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#define CLK_TVE1_CLK 61
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#define CLK_TVD 62
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#define CLK_CSI 63
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#define CLK_VE 64
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#define CLK_CODEC 65
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#define CLK_AVS 66
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#endif
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