/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* Device Tree binding constants clock controllers of Samsung S3C2412.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
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#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
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/*
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* Let each exported clock get a unique index, which is used on DT-enabled
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* platforms to lookup the clock from a clock specifier. These indices are
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* therefore considered an ABI and so must not be changed. This implies
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* that new clocks should be added either in free spaces between clock groups
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* or at the end.
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*/
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/* Core clocks. */
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/* id 1 is reserved */
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#define MPLL 2
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#define UPLL 3
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#define MDIVCLK 4
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#define MSYSCLK 5
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#define USYSCLK 6
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#define HCLK 7
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#define PCLK 8
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#define ARMDIV 9
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#define ARMCLK 10
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/* Special clocks */
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#define SCLK_CAM 16
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#define SCLK_UART 17
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#define SCLK_I2S 18
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#define SCLK_USBD 19
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#define SCLK_USBH 20
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/* pclk-gates */
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#define PCLK_WDT 32
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#define PCLK_SPI 33
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#define PCLK_I2S 34
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#define PCLK_I2C 35
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#define PCLK_ADC 36
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#define PCLK_RTC 37
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#define PCLK_GPIO 38
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#define PCLK_UART2 39
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#define PCLK_UART1 40
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#define PCLK_UART0 41
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#define PCLK_SDI 42
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#define PCLK_PWM 43
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#define PCLK_USBD 44
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/* hclk-gates */
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#define HCLK_HALF 48
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#define HCLK_X2 49
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#define HCLK_SDRAM 50
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#define HCLK_USBH 51
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#define HCLK_LCD 52
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#define HCLK_NAND 53
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#define HCLK_DMA3 54
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#define HCLK_DMA2 55
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#define HCLK_DMA1 56
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#define HCLK_DMA0 57
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/* Total number of clocks. */
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#define NR_CLKS (HCLK_DMA0 + 1)
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#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */
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