/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#ifndef _RK628_CGU_H
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#define _RK628_CGU_H
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#define CGU_CLK_CPLL 1
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#define CGU_CLK_GPLL 2
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#define CGU_CLK_CPLL_MUX 3
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#define CGU_CLK_GPLL_MUX 4
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#define CGU_PCLK_GPIO0 5
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#define CGU_PCLK_GPIO1 6
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#define CGU_PCLK_GPIO2 7
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#define CGU_PCLK_GPIO3 8
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#define CGU_PCLK_TXPHY_CON 9
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#define CGU_PCLK_EFUSE 10
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#define CGU_PCLK_DSI0 11
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#define CGU_PCLK_DSI1 12
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#define CGU_PCLK_CSI 13
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#define CGU_PCLK_HDMITX 14
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#define CGU_PCLK_RXPHY 15
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#define CGU_PCLK_HDMIRX 16
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#define CGU_PCLK_DPRX 17
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#define CGU_PCLK_GVIHOST 18
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#define CGU_CLK_CFG_DPHY0 19
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#define CGU_CLK_CFG_DPHY1 20
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#define CGU_CLK_TXESC 21
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#define CGU_CLK_DPRX_VID 22
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#define CGU_CLK_IMODET 23
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#define CGU_CLK_HDMIRX_AUD 24
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#define CGU_CLK_HDMIRX_CEC 25
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#define CGU_CLK_RX_READ 26
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#define CGU_SCLK_VOP 27
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#define CGU_PCLK_LOGIC 28
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#define CGU_CLK_GPIO_DB0 29
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#define CGU_CLK_GPIO_DB1 30
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#define CGU_CLK_GPIO_DB2 31
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#define CGU_CLK_GPIO_DB3 32
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#define CGU_CLK_I2S_8CH_SRC 33
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#define CGU_CLK_I2S_8CH_FRAC 34
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#define CGU_MCLK_I2S_8CH 35
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#define CGU_I2S_MCLKOUT 36
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#define CGU_BT1120DEC 37
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#define CGU_CLK_TESTOUT 38
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#define CGU_NR_CLKS 39
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#endif
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