/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a774c0 CPG Core Clocks */
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#define R8A774C0_CLK_Z2 0
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#define R8A774C0_CLK_ZG 1
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#define R8A774C0_CLK_ZTR 2
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#define R8A774C0_CLK_ZT 3
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#define R8A774C0_CLK_ZX 4
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#define R8A774C0_CLK_S0D1 5
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#define R8A774C0_CLK_S0D3 6
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#define R8A774C0_CLK_S0D6 7
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#define R8A774C0_CLK_S0D12 8
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#define R8A774C0_CLK_S0D24 9
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#define R8A774C0_CLK_S1D1 10
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#define R8A774C0_CLK_S1D2 11
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#define R8A774C0_CLK_S1D4 12
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#define R8A774C0_CLK_S2D1 13
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#define R8A774C0_CLK_S2D2 14
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#define R8A774C0_CLK_S2D4 15
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#define R8A774C0_CLK_S3D1 16
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#define R8A774C0_CLK_S3D2 17
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#define R8A774C0_CLK_S3D4 18
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#define R8A774C0_CLK_S0D6C 19
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#define R8A774C0_CLK_S3D1C 20
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#define R8A774C0_CLK_S3D2C 21
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#define R8A774C0_CLK_S3D4C 22
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#define R8A774C0_CLK_LB 23
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#define R8A774C0_CLK_CL 24
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#define R8A774C0_CLK_ZB3 25
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#define R8A774C0_CLK_ZB3D2 26
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#define R8A774C0_CLK_CR 27
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#define R8A774C0_CLK_CRD2 28
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#define R8A774C0_CLK_SD0H 29
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#define R8A774C0_CLK_SD0 30
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#define R8A774C0_CLK_SD1H 31
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#define R8A774C0_CLK_SD1 32
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#define R8A774C0_CLK_SD3H 33
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#define R8A774C0_CLK_SD3 34
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#define R8A774C0_CLK_RPC 35
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#define R8A774C0_CLK_RPCD2 36
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#define R8A774C0_CLK_ZA2 37
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#define R8A774C0_CLK_ZA8 38
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#define R8A774C0_CLK_Z2D 39
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#define R8A774C0_CLK_MSO 40
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#define R8A774C0_CLK_R 41
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#define R8A774C0_CLK_OSC 42
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#define R8A774C0_CLK_LV0 43
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#define R8A774C0_CLK_LV1 44
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#define R8A774C0_CLK_CSI0 45
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#define R8A774C0_CLK_CP 46
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#define R8A774C0_CLK_CPEX 47
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#define R8A774C0_CLK_CANFD 48
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#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
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