/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
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/* GPU_CC clock registers */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CRC_AHB_CLK 1
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#define GPU_CC_CX_APB_CLK 2
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#define GPU_CC_CX_GMU_CLK 3
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#define GPU_CC_CX_SNOC_DVM_CLK 4
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#define GPU_CC_CXO_AON_CLK 5
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#define GPU_CC_CXO_CLK 6
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#define GPU_CC_GMU_CLK_SRC 7
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#define GPU_CC_GX_GMU_CLK 8
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#define GPU_CC_PLL1 9
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10
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/* GPU_CC Resets */
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#define GPUCC_GPU_CC_ACD_BCR 0
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#define GPUCC_GPU_CC_CX_BCR 1
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#define GPUCC_GPU_CC_GFX3D_AON_BCR 2
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#define GPUCC_GPU_CC_GMU_BCR 3
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#define GPUCC_GPU_CC_GX_BCR 4
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#define GPUCC_GPU_CC_XO_BCR 5
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/* GPU_CC GDSCRs */
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#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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#endif
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