/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
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/* DISP_CC clock registers */
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#define DISP_CC_MDSS_AHB_CLK 0
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#define DISP_CC_MDSS_AHB_CLK_SRC 1
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#define DISP_CC_MDSS_BYTE0_CLK 2
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
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#define DISP_CC_MDSS_BYTE1_CLK 6
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 9
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#define DISP_CC_MDSS_DP_AUX1_CLK 10
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#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
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#define DISP_CC_MDSS_DP_AUX_CLK 12
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
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#define DISP_CC_MDSS_DP_LINK1_CLK 14
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#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
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#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
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#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
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#define DISP_CC_MDSS_DP_LINK_CLK 18
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19
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#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21
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#define DISP_CC_MDSS_DP_PIXEL1_CLK 22
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#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23
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#define DISP_CC_MDSS_DP_PIXEL2_CLK 24
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#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25
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#define DISP_CC_MDSS_DP_PIXEL_CLK 26
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27
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#define DISP_CC_MDSS_ESC0_CLK 28
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#define DISP_CC_MDSS_ESC0_CLK_SRC 29
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#define DISP_CC_MDSS_ESC1_CLK 30
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#define DISP_CC_MDSS_ESC1_CLK_SRC 31
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#define DISP_CC_MDSS_MDP_CLK 32
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#define DISP_CC_MDSS_MDP_CLK_SRC 33
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#define DISP_CC_MDSS_MDP_LUT_CLK 34
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35
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#define DISP_CC_MDSS_PCLK0_CLK 36
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 37
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#define DISP_CC_MDSS_PCLK1_CLK 38
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 39
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#define DISP_CC_MDSS_ROT_CLK 40
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#define DISP_CC_MDSS_ROT_CLK_SRC 41
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#define DISP_CC_MDSS_RSCC_AHB_CLK 42
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43
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#define DISP_CC_MDSS_VSYNC_CLK 44
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 45
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#define DISP_CC_PLL0 46
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#define DISP_CC_PLL1 47
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/* DISP_CC Reset */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_RSCC_BCR 1
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#endif
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