/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX1_H
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#define __DT_BINDINGS_CLOCK_IMX1_H
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#define IMX1_CLK_DUMMY 0
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#define IMX1_CLK_CLK32 1
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#define IMX1_CLK_CLK16M_EXT 2
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#define IMX1_CLK_CLK16M 3
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#define IMX1_CLK_CLK32_PREMULT 4
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#define IMX1_CLK_PREM 5
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#define IMX1_CLK_MPLL 6
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#define IMX1_CLK_MPLL_GATE 7
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#define IMX1_CLK_SPLL 8
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#define IMX1_CLK_SPLL_GATE 9
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#define IMX1_CLK_MCU 10
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#define IMX1_CLK_FCLK 11
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#define IMX1_CLK_HCLK 12
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#define IMX1_CLK_CLK48M 13
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#define IMX1_CLK_PER1 14
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#define IMX1_CLK_PER2 15
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#define IMX1_CLK_PER3 16
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#define IMX1_CLK_CLKO 17
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#define IMX1_CLK_UART3_GATE 18
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#define IMX1_CLK_SSI2_GATE 19
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#define IMX1_CLK_BROM_GATE 20
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#define IMX1_CLK_DMA_GATE 21
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#define IMX1_CLK_CSI_GATE 22
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#define IMX1_CLK_MMA_GATE 23
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#define IMX1_CLK_USBD_GATE 24
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#define IMX1_CLK_MAX 25
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#endif
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