/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2016-2017 Linaro Ltd.
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*/
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#ifndef __DTS_HI3660_CLOCK_H
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#define __DTS_HI3660_CLOCK_H
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/* fixed rate clocks */
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#define HI3660_CLKIN_SYS 0
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#define HI3660_CLKIN_REF 1
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#define HI3660_CLK_FLL_SRC 2
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#define HI3660_CLK_PPLL0 3
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#define HI3660_CLK_PPLL1 4
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#define HI3660_CLK_PPLL2 5
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#define HI3660_CLK_PPLL3 6
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#define HI3660_CLK_SCPLL 7
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#define HI3660_PCLK 8
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#define HI3660_CLK_UART0_DBG 9
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#define HI3660_CLK_UART6 10
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#define HI3660_OSC32K 11
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#define HI3660_OSC19M 12
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#define HI3660_CLK_480M 13
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#define HI3660_CLK_INV 14
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/* clk in crgctrl */
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#define HI3660_FACTOR_UART3 15
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#define HI3660_CLK_FACTOR_MMC 16
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#define HI3660_CLK_GATE_I2C0 17
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#define HI3660_CLK_GATE_I2C1 18
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#define HI3660_CLK_GATE_I2C2 19
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#define HI3660_CLK_GATE_I2C6 20
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#define HI3660_CLK_DIV_SYSBUS 21
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#define HI3660_CLK_DIV_320M 22
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#define HI3660_CLK_DIV_A53 23
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#define HI3660_CLK_GATE_SPI0 24
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#define HI3660_CLK_GATE_SPI2 25
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#define HI3660_PCIEPHY_REF 26
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#define HI3660_CLK_ABB_USB 27
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#define HI3660_HCLK_GATE_SDIO0 28
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#define HI3660_HCLK_GATE_SD 29
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#define HI3660_CLK_GATE_AOMM 30
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#define HI3660_PCLK_GPIO0 31
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#define HI3660_PCLK_GPIO1 32
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#define HI3660_PCLK_GPIO2 33
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#define HI3660_PCLK_GPIO3 34
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#define HI3660_PCLK_GPIO4 35
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#define HI3660_PCLK_GPIO5 36
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#define HI3660_PCLK_GPIO6 37
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#define HI3660_PCLK_GPIO7 38
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#define HI3660_PCLK_GPIO8 39
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#define HI3660_PCLK_GPIO9 40
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#define HI3660_PCLK_GPIO10 41
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#define HI3660_PCLK_GPIO11 42
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#define HI3660_PCLK_GPIO12 43
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#define HI3660_PCLK_GPIO13 44
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#define HI3660_PCLK_GPIO14 45
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#define HI3660_PCLK_GPIO15 46
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#define HI3660_PCLK_GPIO16 47
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#define HI3660_PCLK_GPIO17 48
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#define HI3660_PCLK_GPIO18 49
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#define HI3660_PCLK_GPIO19 50
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#define HI3660_PCLK_GPIO20 51
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#define HI3660_PCLK_GPIO21 52
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#define HI3660_CLK_GATE_SPI3 53
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#define HI3660_CLK_GATE_I2C7 54
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#define HI3660_CLK_GATE_I2C3 55
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#define HI3660_CLK_GATE_SPI1 56
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#define HI3660_CLK_GATE_UART1 57
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#define HI3660_CLK_GATE_UART2 58
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#define HI3660_CLK_GATE_UART4 59
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#define HI3660_CLK_GATE_UART5 60
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#define HI3660_CLK_GATE_I2C4 61
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#define HI3660_CLK_GATE_DMAC 62
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#define HI3660_PCLK_GATE_DSS 63
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#define HI3660_ACLK_GATE_DSS 64
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#define HI3660_CLK_GATE_LDI1 65
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#define HI3660_CLK_GATE_LDI0 66
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#define HI3660_CLK_GATE_VIVOBUS 67
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#define HI3660_CLK_GATE_EDC0 68
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#define HI3660_CLK_GATE_TXDPHY0_CFG 69
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#define HI3660_CLK_GATE_TXDPHY0_REF 70
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#define HI3660_CLK_GATE_TXDPHY1_CFG 71
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#define HI3660_CLK_GATE_TXDPHY1_REF 72
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#define HI3660_ACLK_GATE_USB3OTG 73
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#define HI3660_CLK_GATE_SPI4 74
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#define HI3660_CLK_GATE_SD 75
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#define HI3660_CLK_GATE_SDIO0 76
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#define HI3660_CLK_GATE_UFS_SUBSYS 77
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#define HI3660_PCLK_GATE_DSI0 78
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#define HI3660_PCLK_GATE_DSI1 79
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#define HI3660_ACLK_GATE_PCIE 80
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#define HI3660_PCLK_GATE_PCIE_SYS 81
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#define HI3660_CLK_GATE_PCIEAUX 82
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#define HI3660_PCLK_GATE_PCIE_PHY 83
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#define HI3660_CLK_ANDGT_LDI0 84
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#define HI3660_CLK_ANDGT_LDI1 85
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#define HI3660_CLK_ANDGT_EDC0 86
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#define HI3660_CLK_GATE_UFSPHY_GT 87
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#define HI3660_CLK_ANDGT_MMC 88
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#define HI3660_CLK_ANDGT_SD 89
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#define HI3660_CLK_A53HPM_ANDGT 90
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#define HI3660_CLK_ANDGT_SDIO 91
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#define HI3660_CLK_ANDGT_UART0 92
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#define HI3660_CLK_ANDGT_UART1 93
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#define HI3660_CLK_ANDGT_UARTH 94
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#define HI3660_CLK_ANDGT_SPI 95
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#define HI3660_CLK_VIVOBUS_ANDGT 96
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#define HI3660_CLK_AOMM_ANDGT 97
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#define HI3660_CLK_320M_PLL_GT 98
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#define HI3660_AUTODIV_EMMC0BUS 99
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#define HI3660_AUTODIV_SYSBUS 100
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#define HI3660_CLK_GATE_UFSPHY_CFG 101
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#define HI3660_CLK_GATE_UFSIO_REF 102
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#define HI3660_CLK_MUX_SYSBUS 103
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#define HI3660_CLK_MUX_UART0 104
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#define HI3660_CLK_MUX_UART1 105
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#define HI3660_CLK_MUX_UARTH 106
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#define HI3660_CLK_MUX_SPI 107
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#define HI3660_CLK_MUX_I2C 108
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#define HI3660_CLK_MUX_MMC_PLL 109
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#define HI3660_CLK_MUX_LDI1 110
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#define HI3660_CLK_MUX_LDI0 111
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#define HI3660_CLK_MUX_SD_PLL 112
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#define HI3660_CLK_MUX_SD_SYS 113
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#define HI3660_CLK_MUX_EDC0 114
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#define HI3660_CLK_MUX_SDIO_SYS 115
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#define HI3660_CLK_MUX_SDIO_PLL 116
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#define HI3660_CLK_MUX_VIVOBUS 117
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#define HI3660_CLK_MUX_A53HPM 118
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#define HI3660_CLK_MUX_320M 119
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#define HI3660_CLK_MUX_IOPERI 120
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#define HI3660_CLK_DIV_UART0 121
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#define HI3660_CLK_DIV_UART1 122
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#define HI3660_CLK_DIV_UARTH 123
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#define HI3660_CLK_DIV_MMC 124
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#define HI3660_CLK_DIV_SD 125
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#define HI3660_CLK_DIV_EDC0 126
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#define HI3660_CLK_DIV_LDI0 127
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#define HI3660_CLK_DIV_SDIO 128
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#define HI3660_CLK_DIV_LDI1 129
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#define HI3660_CLK_DIV_SPI 130
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#define HI3660_CLK_DIV_VIVOBUS 131
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#define HI3660_CLK_DIV_I2C 132
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#define HI3660_CLK_DIV_UFSPHY 133
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#define HI3660_CLK_DIV_CFGBUS 134
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#define HI3660_CLK_DIV_MMC0BUS 135
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#define HI3660_CLK_DIV_MMC1BUS 136
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#define HI3660_CLK_DIV_UFSPERI 137
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#define HI3660_CLK_DIV_AOMM 138
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#define HI3660_CLK_DIV_IOPERI 139
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#define HI3660_VENC_VOLT_HOLD 140
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#define HI3660_PERI_VOLT_HOLD 141
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#define HI3660_CLK_GATE_VENC 142
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#define HI3660_CLK_GATE_VDEC 143
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#define HI3660_CLK_ANDGT_VENC 144
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#define HI3660_CLK_ANDGT_VDEC 145
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#define HI3660_CLK_MUX_VENC 146
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#define HI3660_CLK_MUX_VDEC 147
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#define HI3660_CLK_DIV_VENC 148
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#define HI3660_CLK_DIV_VDEC 149
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#define HI3660_CLK_FAC_ISP_SNCLK 150
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#define HI3660_CLK_GATE_ISP_SNCLK0 151
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#define HI3660_CLK_GATE_ISP_SNCLK1 152
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#define HI3660_CLK_GATE_ISP_SNCLK2 153
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#define HI3660_CLK_ANGT_ISP_SNCLK 154
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#define HI3660_CLK_MUX_ISP_SNCLK 155
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#define HI3660_CLK_DIV_ISP_SNCLK 156
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/* clk in pmuctrl */
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#define HI3660_GATE_ABB_192 0
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/* clk in pctrl */
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#define HI3660_GATE_UFS_TCXO_EN 0
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#define HI3660_GATE_USB_TCXO_EN 1
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/* clk in sctrl */
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#define HI3660_PCLK_AO_GPIO0 0
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#define HI3660_PCLK_AO_GPIO1 1
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#define HI3660_PCLK_AO_GPIO2 2
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#define HI3660_PCLK_AO_GPIO3 3
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#define HI3660_PCLK_AO_GPIO4 4
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#define HI3660_PCLK_AO_GPIO5 5
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#define HI3660_PCLK_AO_GPIO6 6
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#define HI3660_PCLK_GATE_MMBUF 7
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#define HI3660_CLK_GATE_DSS_AXI_MM 8
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#define HI3660_PCLK_MMBUF_ANDGT 9
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#define HI3660_CLK_MMBUF_PLL_ANDGT 10
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#define HI3660_CLK_FLL_MMBUF_ANDGT 11
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#define HI3660_CLK_SYS_MMBUF_ANDGT 12
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#define HI3660_CLK_GATE_PCIEPHY_GT 13
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#define HI3660_ACLK_MUX_MMBUF 14
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#define HI3660_CLK_SW_MMBUF 15
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#define HI3660_CLK_DIV_AOBUS 16
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#define HI3660_PCLK_DIV_MMBUF 17
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#define HI3660_ACLK_DIV_MMBUF 18
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#define HI3660_CLK_DIV_PCIEPHY 19
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/* clk in iomcu */
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#define HI3660_CLK_I2C0_IOMCU 0
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#define HI3660_CLK_I2C1_IOMCU 1
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#define HI3660_CLK_I2C2_IOMCU 2
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#define HI3660_CLK_I2C6_IOMCU 3
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#define HI3660_CLK_IOMCU_PERI0 4
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/* clk in stub clock */
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#define HI3660_CLK_STUB_CLUSTER0 0
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#define HI3660_CLK_STUB_CLUSTER1 1
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#define HI3660_CLK_STUB_GPU 2
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#define HI3660_CLK_STUB_DDR 3
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#define HI3660_CLK_STUB_NUM 4
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#endif /* __DTS_HI3660_CLOCK_H */
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