/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2012-2013 Hisilicon Limited.
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* Copyright (c) 2012-2013 Linaro Limited.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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* Xin Li <li.xin@linaro.org>
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*/
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#ifndef __DTS_HI3620_CLOCK_H
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#define __DTS_HI3620_CLOCK_H
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#define HI3620_NONE_CLOCK 0
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/* fixed rate & fixed factor clocks */
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#define HI3620_OSC32K 1
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#define HI3620_OSC26M 2
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#define HI3620_PCLK 3
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#define HI3620_PLL_ARM0 4
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#define HI3620_PLL_ARM1 5
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#define HI3620_PLL_PERI 6
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#define HI3620_PLL_USB 7
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#define HI3620_PLL_HDMI 8
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#define HI3620_PLL_GPU 9
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#define HI3620_RCLK_TCXO 10
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#define HI3620_RCLK_CFGAXI 11
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#define HI3620_RCLK_PICO 12
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/* mux clocks */
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#define HI3620_TIMER0_MUX 32
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#define HI3620_TIMER1_MUX 33
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#define HI3620_TIMER2_MUX 34
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#define HI3620_TIMER3_MUX 35
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#define HI3620_TIMER4_MUX 36
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#define HI3620_TIMER5_MUX 37
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#define HI3620_TIMER6_MUX 38
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#define HI3620_TIMER7_MUX 39
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#define HI3620_TIMER8_MUX 40
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#define HI3620_TIMER9_MUX 41
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#define HI3620_UART0_MUX 42
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#define HI3620_UART1_MUX 43
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#define HI3620_UART2_MUX 44
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#define HI3620_UART3_MUX 45
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#define HI3620_UART4_MUX 46
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#define HI3620_SPI0_MUX 47
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#define HI3620_SPI1_MUX 48
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#define HI3620_SPI2_MUX 49
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#define HI3620_SAXI_MUX 50
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#define HI3620_PWM0_MUX 51
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#define HI3620_PWM1_MUX 52
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#define HI3620_SD_MUX 53
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#define HI3620_MMC1_MUX 54
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#define HI3620_MMC1_MUX2 55
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#define HI3620_G2D_MUX 56
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#define HI3620_VENC_MUX 57
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#define HI3620_VDEC_MUX 58
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#define HI3620_VPP_MUX 59
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#define HI3620_EDC0_MUX 60
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#define HI3620_LDI0_MUX 61
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#define HI3620_EDC1_MUX 62
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#define HI3620_LDI1_MUX 63
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#define HI3620_RCLK_HSIC 64
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#define HI3620_MMC2_MUX 65
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#define HI3620_MMC3_MUX 66
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/* divider clocks */
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#define HI3620_SHAREAXI_DIV 128
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#define HI3620_CFGAXI_DIV 129
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#define HI3620_SD_DIV 130
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#define HI3620_MMC1_DIV 131
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#define HI3620_HSIC_DIV 132
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#define HI3620_MMC2_DIV 133
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#define HI3620_MMC3_DIV 134
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/* gate clocks */
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#define HI3620_TIMERCLK01 160
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#define HI3620_TIMER_RCLK01 161
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#define HI3620_TIMERCLK23 162
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#define HI3620_TIMER_RCLK23 163
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#define HI3620_TIMERCLK45 164
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#define HI3620_TIMERCLK67 165
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#define HI3620_TIMERCLK89 166
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#define HI3620_RTCCLK 167
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#define HI3620_KPC_CLK 168
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#define HI3620_GPIOCLK0 169
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#define HI3620_GPIOCLK1 170
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#define HI3620_GPIOCLK2 171
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#define HI3620_GPIOCLK3 172
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#define HI3620_GPIOCLK4 173
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#define HI3620_GPIOCLK5 174
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#define HI3620_GPIOCLK6 175
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#define HI3620_GPIOCLK7 176
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#define HI3620_GPIOCLK8 177
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#define HI3620_GPIOCLK9 178
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#define HI3620_GPIOCLK10 179
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#define HI3620_GPIOCLK11 180
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#define HI3620_GPIOCLK12 181
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#define HI3620_GPIOCLK13 182
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#define HI3620_GPIOCLK14 183
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#define HI3620_GPIOCLK15 184
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#define HI3620_GPIOCLK16 185
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#define HI3620_GPIOCLK17 186
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#define HI3620_GPIOCLK18 187
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#define HI3620_GPIOCLK19 188
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#define HI3620_GPIOCLK20 189
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#define HI3620_GPIOCLK21 190
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#define HI3620_DPHY0_CLK 191
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#define HI3620_DPHY1_CLK 192
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#define HI3620_DPHY2_CLK 193
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#define HI3620_USBPHY_CLK 194
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#define HI3620_ACP_CLK 195
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#define HI3620_PWMCLK0 196
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#define HI3620_PWMCLK1 197
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#define HI3620_UARTCLK0 198
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#define HI3620_UARTCLK1 199
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#define HI3620_UARTCLK2 200
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#define HI3620_UARTCLK3 201
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#define HI3620_UARTCLK4 202
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#define HI3620_SPICLK0 203
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#define HI3620_SPICLK1 204
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#define HI3620_SPICLK2 205
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#define HI3620_I2CCLK0 206
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#define HI3620_I2CCLK1 207
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#define HI3620_I2CCLK2 208
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#define HI3620_I2CCLK3 209
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#define HI3620_SCI_CLK 210
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#define HI3620_DDRC_PER_CLK 211
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#define HI3620_DMAC_CLK 212
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#define HI3620_USB2DVC_CLK 213
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#define HI3620_SD_CLK 214
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#define HI3620_MMC_CLK1 215
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#define HI3620_MMC_CLK2 216
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#define HI3620_MMC_CLK3 217
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#define HI3620_MCU_CLK 218
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#define HI3620_SD_CIUCLK 0
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#define HI3620_MMC_CIUCLK1 1
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#define HI3620_MMC_CIUCLK2 2
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#define HI3620_MMC_CIUCLK3 3
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#define HI3620_NR_CLKS 219
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#endif /* __DTS_HI3620_CLOCK_H */
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