// SPDX-License-Identifier: GPL-2.0+
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//
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// Device Tree binding constants for Actions Semi S900 Clock Management Unit
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Copyright (c) 2018 Linaro Ltd.
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#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
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#define __DT_BINDINGS_CLOCK_S900_CMU_H
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#define CLK_NONE 0
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/* fixed rate clocks */
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#define CLK_LOSC 1
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#define CLK_HOSC 2
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/* pll clocks */
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#define CLK_CORE_PLL 3
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#define CLK_DEV_PLL 4
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#define CLK_DDR_PLL 5
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#define CLK_NAND_PLL 6
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#define CLK_DISPLAY_PLL 7
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#define CLK_DSI_PLL 8
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#define CLK_ASSIST_PLL 9
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#define CLK_AUDIO_PLL 10
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/* system clock */
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#define CLK_CPU 15
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#define CLK_DEV 16
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#define CLK_NOC 17
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#define CLK_NOC_MUX 18
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#define CLK_NOC_DIV 19
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#define CLK_AHB 20
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#define CLK_APB 21
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#define CLK_DMAC 22
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/* peripheral device clock */
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#define CLK_GPIO 23
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#define CLK_BISP 24
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#define CLK_CSI0 25
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#define CLK_CSI1 26
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#define CLK_DE0 27
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#define CLK_DE1 28
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#define CLK_DE2 29
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#define CLK_DE3 30
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#define CLK_DSI 32
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#define CLK_GPU 33
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#define CLK_GPU_CORE 34
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#define CLK_GPU_MEM 35
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#define CLK_GPU_SYS 36
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#define CLK_HDE 37
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#define CLK_I2C0 38
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#define CLK_I2C1 39
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#define CLK_I2C2 40
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#define CLK_I2C3 41
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#define CLK_I2C4 42
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#define CLK_I2C5 43
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#define CLK_I2SRX 44
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#define CLK_I2STX 45
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#define CLK_IMX 46
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#define CLK_LCD 47
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#define CLK_NAND0 48
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#define CLK_NAND1 49
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#define CLK_PWM0 50
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#define CLK_PWM1 51
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#define CLK_PWM2 52
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#define CLK_PWM3 53
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#define CLK_PWM4 54
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#define CLK_PWM5 55
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#define CLK_SD0 56
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#define CLK_SD1 57
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#define CLK_SD2 58
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#define CLK_SD3 59
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#define CLK_SENSOR 60
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#define CLK_SPEED_SENSOR 61
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#define CLK_SPI0 62
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#define CLK_SPI1 63
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#define CLK_SPI2 64
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#define CLK_SPI3 65
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#define CLK_THERMAL_SENSOR 66
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#define CLK_UART0 67
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#define CLK_UART1 68
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#define CLK_UART2 69
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#define CLK_UART3 70
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#define CLK_UART4 71
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#define CLK_UART5 72
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#define CLK_UART6 73
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#define CLK_VCE 74
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#define CLK_VDE 75
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#define CLK_USB3_480MPLL0 76
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#define CLK_USB3_480MPHY0 77
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#define CLK_USB3_5GPHY 78
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#define CLK_USB3_CCE 79
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#define CLK_USB3_MAC 80
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#define CLK_TIMER 83
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#define CLK_HDMI_AUDIO 84
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#define CLK_24M 85
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#define CLK_EDP 86
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#define CLK_24M_EDP 87
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#define CLK_EDP_PLL 88
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#define CLK_EDP_LINK 89
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#define CLK_USB2H0_PLLEN 90
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#define CLK_USB2H0_PHY 91
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#define CLK_USB2H0_CCE 92
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#define CLK_USB2H1_PLLEN 93
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#define CLK_USB2H1_PHY 94
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#define CLK_USB2H1_CCE 95
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#define CLK_DDR0 96
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#define CLK_DDR1 97
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#define CLK_DMM 98
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#define CLK_ETH_MAC 99
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#define CLK_RMII_REF 100
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#define CLK_NR_CLKS (CLK_RMII_REF + 1)
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#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
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