// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas USB driver R-Car Gen. 3 initialization and power control
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*
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* Copyright (C) 2016-2019 Renesas Electronics Corporation
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "common.h"
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#include "rcar3.h"
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#define LPSTS 0x102
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#define UGCTRL 0x180 /* 32-bit register */
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#define UGCTRL2 0x184 /* 32-bit register */
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#define UGSTS 0x188 /* 32-bit register */
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/* Low Power Status register (LPSTS) */
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#define LPSTS_SUSPM 0x4000
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/* R-Car D3 only: USB General control register (UGCTRL) */
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#define UGCTRL_PLLRESET 0x00000001
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#define UGCTRL_CONNECT 0x00000004
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/*
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* USB General control register 2 (UGCTRL2)
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* Remarks: bit[31:11] and bit[9:6] should be 0
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*/
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#define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
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#define UGCTRL2_USB0SEL_HSUSB 0x00000020
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#define UGCTRL2_USB0SEL_OTG 0x00000030
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#define UGCTRL2_VBUSSEL 0x00000400
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/* R-Car D3 only: USB General status register (UGSTS) */
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#define UGSTS_LOCK 0x00000100
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static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
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{
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iowrite32(data, priv->base + reg);
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}
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static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
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{
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return ioread32(priv->base + reg);
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}
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static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val)
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{
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usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3);
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}
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static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
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void __iomem *base, int enable)
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{
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struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
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usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
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if (enable) {
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
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/* The controller on R-Car Gen3 needs to wait up to 45 usec */
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usleep_range(45, 90);
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} else {
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
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}
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return 0;
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}
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/* R-Car D3 needs to release UGCTRL.PLLRESET */
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static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
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void __iomem *base, int enable)
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{
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struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
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u32 val;
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int timeout = 1000;
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if (enable) {
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usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */
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usbhs_rcar3_set_ugctrl2(priv,
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UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
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do {
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val = usbhs_read32(priv, UGSTS);
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udelay(1);
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} while (!(val & UGSTS_LOCK) && timeout--);
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usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT);
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} else {
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usbhs_write32(priv, UGCTRL, 0);
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
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usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET);
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}
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return 0;
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}
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const struct renesas_usbhs_platform_info usbhs_rcar_gen3_plat_info = {
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.platform_callback = {
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.power_ctrl = usbhs_rcar3_power_ctrl,
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.get_id = usbhs_get_id_as_gadget,
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},
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.driver_param = {
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.has_usb_dmac = 1,
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.multi_clks = 1,
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.has_new_pipe_configs = 1,
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},
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};
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const struct renesas_usbhs_platform_info usbhs_rcar_gen3_with_pll_plat_info = {
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.platform_callback = {
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.power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
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.get_id = usbhs_get_id_as_gadget,
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},
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.driver_param = {
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.has_usb_dmac = 1,
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.multi_clks = 1,
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.has_new_pipe_configs = 1,
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},
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};
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