/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* Author:
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* Wei WANG (wei_wang@realsil.com.cn)
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* Micky Ching (micky_ching@realsil.com.cn)
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*/
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#ifndef __REALTEK_RTSX_XD_H
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#define __REALTEK_RTSX_XD_H
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#define XD_DELAY_WRITE
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/* Error Codes */
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#define XD_NO_ERROR 0x00
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#define XD_NO_MEMORY 0x80
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#define XD_PRG_ERROR 0x40
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#define XD_NO_CARD 0x20
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#define XD_READ_FAIL 0x10
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#define XD_ERASE_FAIL 0x08
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#define XD_WRITE_FAIL 0x04
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#define XD_ECC_ERROR 0x02
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#define XD_TO_ERROR 0x01
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/* XD Commands */
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#define READ1_1 0x00
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#define READ1_2 0x01
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#define READ2 0x50
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#define READ_ID 0x90
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#define RESET 0xff
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#define PAGE_PRG_1 0x80
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#define PAGE_PRG_2 0x10
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#define BLK_ERASE_1 0x60
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#define BLK_ERASE_2 0xD0
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#define READ_STS 0x70
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#define READ_XD_ID 0x9A
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#define COPY_BACK_512 0x8A
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#define COPY_BACK_2K 0x85
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#define READ1_1_2 0x30
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#define READ1_1_3 0x35
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#define CHG_DAT_OUT_1 0x05
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#define RDM_DAT_OUT_1 0x05
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#define CHG_DAT_OUT_2 0xE0
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#define RDM_DAT_OUT_2 0xE0
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#define CHG_DAT_OUT_2 0xE0
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#define CHG_DAT_IN_1 0x85
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#define CACHE_PRG 0x15
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/* Redundant Area Related */
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#define XD_EXTRA_SIZE 0x10
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#define XD_2K_EXTRA_SIZE 0x40
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#define NOT_WRITE_PROTECTED 0x80
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#define READY_STATE 0x40
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#define PROGRAM_ERROR 0x01
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#define PROGRAM_ERROR_N_1 0x02
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#define INTERNAL_READY 0x20
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#define READY_FLAG 0x5F
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#define XD_8M_X8_512 0xE6
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#define XD_16M_X8_512 0x73
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#define XD_32M_X8_512 0x75
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#define XD_64M_X8_512 0x76
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#define XD_128M_X8_512 0x79
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#define XD_256M_X8_512 0x71
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#define XD_128M_X8_2048 0xF1
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#define XD_256M_X8_2048 0xDA
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#define XD_512M_X8 0xDC
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#define XD_128M_X16_2048 0xC1
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#define XD_4M_X8_512_1 0xE3
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#define XD_4M_X8_512_2 0xE5
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#define XD_1G_X8_512 0xD3
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#define XD_2G_X8_512 0xD5
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#define XD_ID_CODE 0xB5
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#define VENDOR_BLOCK 0xEFFF
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#define CIS_BLOCK 0xDFFF
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#define BLK_NOT_FOUND 0xFFFFFFFF
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#define NO_NEW_BLK 0xFFFFFFFF
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#define PAGE_CORRECTABLE 0x0
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#define PAGE_NOTCORRECTABLE 0x1
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#define NO_OFFSET 0x0
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#define WITH_OFFSET 0x1
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#define SECT_PER_PAGE 4
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#define XD_ADDR_MODE_2C XD_ADDR_MODE_2A
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#define ZONE0_BAD_BLOCK 23
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#define NOT_ZONE0_BAD_BLOCK 24
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#define XD_RW_ADDR 0x01
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#define XD_ERASE_ADDR 0x02
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#define XD_PAGE_512(xd_card) \
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do { \
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(xd_card)->block_shift = 5; \
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(xd_card)->page_off = 0x1F; \
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} while (0)
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#define XD_SET_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag |= 0x01)
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#define XD_CLR_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag &= ~0x01)
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#define XD_CHK_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag & 0x01)
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#define XD_SET_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag |= 0x02)
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#define XD_CLR_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag &= ~0x02)
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#define XD_CHK_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag & 0x02)
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#define XD_SET_MBR_FAIL(xd_card) ((xd_card)->multi_flag |= 0x04)
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#define XD_CLR_MBR_FAIL(xd_card) ((xd_card)->multi_flag &= ~0x04)
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#define XD_CHK_MBR_FAIL(xd_card) ((xd_card)->multi_flag & 0x04)
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#define XD_SET_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag |= 0x08)
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#define XD_CLR_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag &= ~0x08)
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#define XD_CHK_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag & 0x08)
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#define XD_SET_4MB(xd_card) ((xd_card)->multi_flag |= 0x10)
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#define XD_CLR_4MB(xd_card) ((xd_card)->multi_flag &= ~0x10)
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#define XD_CHK_4MB(xd_card) ((xd_card)->multi_flag & 0x10)
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#define XD_SET_ECC_ERR(xd_card) ((xd_card)->multi_flag |= 0x40)
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#define XD_CLR_ECC_ERR(xd_card) ((xd_card)->multi_flag &= ~0x40)
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#define XD_CHK_ECC_ERR(xd_card) ((xd_card)->multi_flag & 0x40)
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#define PAGE_STATUS 0
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#define BLOCK_STATUS 1
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#define BLOCK_ADDR1_L 2
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#define BLOCK_ADDR1_H 3
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#define BLOCK_ADDR2_L 4
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#define BLOCK_ADDR2_H 5
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#define RESERVED0 6
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#define RESERVED1 7
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#define RESERVED2 8
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#define RESERVED3 9
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#define PARITY 10
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#define CIS0_0 0
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#define CIS0_1 1
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#define CIS0_2 2
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#define CIS0_3 3
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#define CIS0_4 4
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#define CIS0_5 5
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#define CIS0_6 6
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#define CIS0_7 7
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#define CIS0_8 8
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#define CIS0_9 9
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#define CIS1_0 256
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#define CIS1_1 (256 + 1)
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#define CIS1_2 (256 + 2)
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#define CIS1_3 (256 + 3)
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#define CIS1_4 (256 + 4)
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#define CIS1_5 (256 + 5)
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#define CIS1_6 (256 + 6)
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#define CIS1_7 (256 + 7)
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#define CIS1_8 (256 + 8)
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#define CIS1_9 (256 + 9)
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int reset_xd_card(struct rtsx_chip *chip);
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#ifdef XD_DELAY_WRITE
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int xd_delay_write(struct rtsx_chip *chip);
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#endif
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int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
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u32 start_sector, u16 sector_cnt);
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void xd_free_l2p_tbl(struct rtsx_chip *chip);
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void xd_cleanup_work(struct rtsx_chip *chip);
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int xd_power_off_card3v3(struct rtsx_chip *chip);
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int release_xd_card(struct rtsx_chip *chip);
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#endif /* __REALTEK_RTSX_XD_H */
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