/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#ifndef __HAL_DATA_H__
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#define __HAL_DATA_H__
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#include "odm_precomp.h"
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#include <hal_btcoex.h>
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#include <hal_sdio.h>
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/* */
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/* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
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/* */
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enum RT_MULTI_FUNC {
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RT_MULTI_FUNC_NONE = 0x00,
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RT_MULTI_FUNC_WIFI = 0x01,
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RT_MULTI_FUNC_BT = 0x02,
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RT_MULTI_FUNC_GPS = 0x04,
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};
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/* */
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/* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
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/* */
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enum RT_POLARITY_CTL {
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RT_POLARITY_LOW_ACT = 0,
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RT_POLARITY_HIGH_ACT = 1,
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};
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/* For RTL8723 regulator mode. by tynli. 2011.01.14. */
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enum RT_REGULATOR_MODE {
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RT_SWITCHING_REGULATOR = 0,
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RT_LDO_REGULATOR = 1,
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};
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enum RT_AMPDU_BURST {
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RT_AMPDU_BURST_NONE = 0,
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RT_AMPDU_BURST_92D = 1,
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RT_AMPDU_BURST_88E = 2,
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RT_AMPDU_BURST_8812_4 = 3,
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RT_AMPDU_BURST_8812_8 = 4,
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RT_AMPDU_BURST_8812_12 = 5,
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RT_AMPDU_BURST_8812_15 = 6,
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RT_AMPDU_BURST_8723B = 7,
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};
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#define CHANNEL_MAX_NUMBER 14+24+21 /* 14 is the max channel number */
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#define CHANNEL_MAX_NUMBER_2G 14
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#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A" */
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#define CHANNEL_MAX_NUMBER_5G_80M 7
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#define CHANNEL_GROUP_MAX 3+9 /* ch1~3, ch4~9, ch10~14 total three groups */
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#define MAX_PG_GROUP 13
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/* Tx Power Limit Table Size */
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#define MAX_REGULATION_NUM 4
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#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4
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#define MAX_2_4G_BANDWIDTH_NUM 4
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#define MAX_RATE_SECTION_NUM 10
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#define MAX_5G_BANDWIDTH_NUM 4
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#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
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#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */
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/* duplicate code, will move to ODM ######### */
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/* define IQK_MAC_REG_NUM 4 */
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/* define IQK_ADDA_REG_NUM 16 */
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/* define IQK_BB_REG_NUM 10 */
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#define IQK_BB_REG_NUM_92C 9
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#define IQK_BB_REG_NUM_92D 10
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#define IQK_BB_REG_NUM_test 6
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#define IQK_Matrix_Settings_NUM_92D 1+24+21
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/* define HP_THERMAL_NUM 8 */
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/* duplicate code, will move to ODM ######### */
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enum {
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SINGLEMAC_SINGLEPHY, /* SMSP */
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DUALMAC_DUALPHY, /* DMDP */
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DUALMAC_SINGLEPHY, /* DMSP */
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};
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#define PAGE_SIZE_128 128
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#define PAGE_SIZE_256 256
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#define PAGE_SIZE_512 512
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struct dm_priv {
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u8 DM_Type;
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#define DYNAMIC_FUNC_BT BIT0
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u8 DMFlag;
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u8 InitDMFlag;
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/* u8 RSVD_1; */
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u32 InitODMFlag;
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/* Upper and Lower Signal threshold for Rate Adaptive */
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int UndecoratedSmoothedPWDB;
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int UndecoratedSmoothedCCK;
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int EntryMinUndecoratedSmoothedPWDB;
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int EntryMaxUndecoratedSmoothedPWDB;
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int MinUndecoratedPWDBForDM;
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int LastMinUndecoratedPWDBForDM;
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s32 UndecoratedSmoothedBeacon;
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/* duplicate code, will move to ODM ######### */
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/* for High Power */
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u8 bDynamicTxPowerEnable;
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u8 LastDTPLvl;
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u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */
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/* for tx power tracking */
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u8 bTXPowerTracking;
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u8 TXPowercount;
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u8 bTXPowerTrackingInit;
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u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
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u8 TM_Trigger;
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u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
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u8 ThermalValue;
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u8 ThermalValue_LCK;
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u8 ThermalValue_IQK;
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u8 ThermalValue_DPK;
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u8 bRfPiEnable;
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/* u8 RSVD_2; */
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/* for APK */
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u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
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u8 bAPKdone;
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u8 bAPKThermalMeterIgnore;
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u8 bDPdone;
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u8 bDPPathAOK;
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u8 bDPPathBOK;
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/* u8 RSVD_3; */
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/* u8 RSVD_4; */
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/* u8 RSVD_5; */
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/* for IQK */
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u32 ADDA_backup[IQK_ADDA_REG_NUM];
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u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
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u32 IQK_BB_backup_recover[9];
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u32 IQK_BB_backup[IQK_BB_REG_NUM];
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u8 PowerIndex_backup[6];
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u8 OFDM_index[2];
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u8 bCCKinCH14;
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u8 CCK_index;
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u8 bDoneTxpower;
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u8 CCK_index_HP;
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u8 OFDM_index_HP[2];
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u8 ThermalValue_HP[HP_THERMAL_NUM];
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u8 ThermalValue_HP_index;
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/* u8 RSVD_6; */
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/* for TxPwrTracking2 */
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s32 RegE94;
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s32 RegE9C;
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s32 RegEB4;
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s32 RegEBC;
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u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
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u32 prv_traffic_idx; /* edca turbo */
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/* duplicate code, will move to ODM ######### */
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/* Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas */
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u8 INIDATA_RATE[32];
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};
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struct hal_com_data {
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HAL_VERSION VersionID;
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enum RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */
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enum RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */
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enum RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */
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u16 FirmwareVersion;
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u16 FirmwareVersionRev;
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u16 FirmwareSubVersion;
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u16 FirmwareSignature;
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/* current WIFI_PHY values */
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enum WIRELESS_MODE CurrentWirelessMode;
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enum CHANNEL_WIDTH CurrentChannelBW;
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enum BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */
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enum BAND_TYPE BandSet;
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u8 CurrentChannel;
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u8 CurrentCenterFrequencyIndex1;
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u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
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u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */
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u16 CustomerID;
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u16 BasicRateSet;
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u16 ForcedDataRate;/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
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u32 ReceiveConfig;
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/* rf_ctrl */
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u8 rf_chip;
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u8 rf_type;
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u8 PackageType;
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u8 NumTotalRFPath;
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u8 InterfaceSel;
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u8 framesync;
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u32 framesyncC34;
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u8 framesyncMonitor;
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u8 DefaultInitialGain[4];
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/* EEPROM setting. */
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u16 EEPROMVID;
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u16 EEPROMSVID;
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u8 EEPROMCustomerID;
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u8 EEPROMSubCustomerID;
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u8 EEPROMVersion;
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u8 EEPROMRegulatory;
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u8 EEPROMThermalMeter;
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u8 EEPROMBluetoothCoexist;
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u8 EEPROMBluetoothType;
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u8 EEPROMBluetoothAntNum;
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u8 EEPROMBluetoothAntIsolation;
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u8 EEPROMBluetoothRadioShared;
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u8 bTXPowerDataReadFromEEPORM;
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u8 bAPKThermalMeterIgnore;
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u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */
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bool EepromOrEfuse;
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u8 EfuseUsedPercentage;
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u16 EfuseUsedBytes;
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EFUSE_HAL EfuseHal;
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/* 3 [2.4G] */
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u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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/* If only one tx, only BW20 and OFDM are used. */
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s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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/* 3 [5G] */
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u8 Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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u8 Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
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s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 Regulation2_4G;
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u8 Regulation5G;
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u8 TxPwrInPercentage;
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u8 TxPwrCalibrateRate;
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/* TX power by rate table at most 4RF path. */
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/* The register is */
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/* VHT TX power by rate off setArray = */
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/* Band:-2G&5G = 0 / 1 */
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/* RF: at most 4*4 = ABCD = 0/1/2/3 */
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/* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */
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u8 TxPwrByRateTable;
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u8 TxPwrByRateBand;
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s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
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[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RATE];
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/* */
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/* 2 Power Limit Table */
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u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
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u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
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u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
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s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */
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u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */
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/* Power Limit Table for 2.4G */
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s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
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[MAX_2_4G_BANDWIDTH_NUM]
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[MAX_RATE_SECTION_NUM]
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[CHANNEL_MAX_NUMBER_2G]
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[MAX_RF_PATH_NUM];
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/* Power Limit Table for 5G */
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s8 TxPwrLimit_5G[MAX_REGULATION_NUM]
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[MAX_5G_BANDWIDTH_NUM]
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[MAX_RATE_SECTION_NUM]
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[CHANNEL_MAX_NUMBER_5G]
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[MAX_RF_PATH_NUM];
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/* Store the original power by rate value of the base of each rate section of rf path A & B */
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u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
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u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
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/* For power group */
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u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
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u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
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u8 PGMaxGroup;
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u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */
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/* The current Tx Power Level */
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u8 CurrentCckTxPwrIdx;
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u8 CurrentOfdm24GTxPwrIdx;
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u8 CurrentBW2024GTxPwrIdx;
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u8 CurrentBW4024GTxPwrIdx;
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/* Read/write are allow for following hardware information variables */
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u8 pwrGroupCnt;
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u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
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u32 CCKTxPowerLevelOriginalOffset;
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u8 CrystalCap;
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u32 AntennaTxPath; /* Antenna path Tx */
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u32 AntennaRxPath; /* Antenna path Rx */
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u8 PAType_2G;
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u8 PAType_5G;
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u8 LNAType_2G;
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u8 LNAType_5G;
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u8 ExternalPA_2G;
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u8 ExternalLNA_2G;
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u8 ExternalPA_5G;
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u8 ExternalLNA_5G;
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u8 TypeGLNA;
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u8 TypeGPA;
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u8 TypeALNA;
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u8 TypeAPA;
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u8 RFEType;
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u8 BoardType;
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u8 ExternalPA;
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u8 bIQKInitialized;
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bool bLCKInProgress;
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bool bSwChnl;
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bool bSetChnlBW;
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bool bChnlBWInitialized;
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bool bNeedIQK;
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u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
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u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
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u8 b1x1RecvCombine; /* for 1T1R receive combining */
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u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
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struct bb_register_def PHYRegDef[4]; /* Radio A/B/C/D */
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u32 RfRegChnlVal[2];
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/* RDG enable */
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bool bRDGEnable;
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/* for host message to fw */
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u8 LastHMEBoxNum;
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u8 fw_ractrl;
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u8 RegTxPause;
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/* Beacon function related global variable. */
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u8 RegBcnCtrlVal;
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u8 RegFwHwTxQCtrl;
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u8 RegReg542;
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u8 RegCR_1;
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u8 Reg837;
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u8 RegRFPathS1;
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u16 RegRRSR;
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u8 CurAntenna;
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u8 AntDivCfg;
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u8 AntDetection;
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u8 TRxAntDivType;
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u8 ant_path; /* for 8723B s0/s1 selection */
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u8 u1ForcedIgiLb; /* forced IGI lower bound */
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u8 bDumpRxPkt;/* for debug */
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u8 bDumpTxPkt;/* for debug */
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u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
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/* 2010/08/09 MH Add CU power down mode. */
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bool pwrdown;
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/* Add for dual MAC 0--Mac0 1--Mac1 */
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u32 interfaceIndex;
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u8 OutEpQueueSel;
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u8 OutEpNumber;
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/* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
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bool UsbRxHighSpeedMode;
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/* 2010/11/22 MH Add for slim combo debug mode selective. */
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/* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */
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bool SlimComboDbg;
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/* u8 AMPDUDensity; */
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/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
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u8 bMacPwrCtrlOn;
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u8 RegIQKFWOffload;
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struct submit_ctx iqk_sctx;
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enum RT_AMPDU_BURST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
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u32 sdio_himr;
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u32 sdio_hisr;
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/* SDIO Tx FIFO related. */
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/* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
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u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
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_lock SdioTxFIFOFreePageLock;
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u8 SdioTxOQTMaxFreeSpace;
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u8 SdioTxOQTFreeSpace;
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/* SDIO Rx FIFO related. */
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u8 SdioRxFIFOCnt;
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u16 SdioRxFIFOSize;
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u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
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struct dm_priv dmpriv;
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DM_ODM_T odmpriv;
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/* For bluetooth co-existance */
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BT_COEXIST bt_coexist;
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/* Interrupt related register information. */
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u32 SysIntrStatus;
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u32 SysIntrMask;
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#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
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s16 noise[ODM_MAX_CHANNEL_NUM];
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#endif
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};
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#define GET_HAL_DATA(__padapter) ((struct hal_com_data *)((__padapter)->HalData))
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#define GET_HAL_RFPATH_NUM(__padapter) (((struct hal_com_data *)((__padapter)->HalData))->NumTotalRFPath)
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#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
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#define GET_RF_TYPE(__padapter) (GET_HAL_DATA(__padapter)->rf_type)
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#endif /* __HAL_DATA_H__ */
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