/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* register description for HopeRf rf69 radio module
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*
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* Copyright (C) 2016 Wolf-Entwicklungen
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* Marcus Wolf <linux@wolf-entwicklungen.de>
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*/
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/*******************************************/
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/* RF69 register addresses */
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/*******************************************/
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#define REG_FIFO 0x00
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#define REG_OPMODE 0x01
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#define REG_DATAMODUL 0x02
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#define REG_BITRATE_MSB 0x03
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#define REG_BITRATE_LSB 0x04
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#define REG_FDEV_MSB 0x05
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#define REG_FDEV_LSB 0x06
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#define REG_FRF_MSB 0x07
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#define REG_FRF_MID 0x08
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#define REG_FRF_LSB 0x09
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#define REG_OSC1 0x0A
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#define REG_AFCCTRL 0x0B
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#define REG_LOWBAT 0x0C
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#define REG_LISTEN1 0x0D
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#define REG_LISTEN2 0x0E
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#define REG_LISTEN3 0x0F
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#define REG_VERSION 0x10
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#define REG_PALEVEL 0x11
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#define REG_PARAMP 0x12
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#define REG_OCP 0x13
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#define REG_AGCREF 0x14 /* not available on RF69 */
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#define REG_AGCTHRESH1 0x15 /* not available on RF69 */
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#define REG_AGCTHRESH2 0x16 /* not available on RF69 */
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#define REG_AGCTHRESH3 0x17 /* not available on RF69 */
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#define REG_LNA 0x18
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#define REG_RXBW 0x19
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#define REG_AFCBW 0x1A
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#define REG_OOKPEAK 0x1B
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#define REG_OOKAVG 0x1C
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#define REG_OOKFIX 0x1D
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#define REG_AFCFEI 0x1E
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#define REG_AFCMSB 0x1F
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#define REG_AFCLSB 0x20
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#define REG_FEIMSB 0x21
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#define REG_FEILSB 0x22
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#define REG_RSSICONFIG 0x23
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#define REG_RSSIVALUE 0x24
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#define REG_DIOMAPPING1 0x25
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#define REG_DIOMAPPING2 0x26
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#define REG_IRQFLAGS1 0x27
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#define REG_IRQFLAGS2 0x28
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#define REG_RSSITHRESH 0x29
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#define REG_RXTIMEOUT1 0x2A
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#define REG_RXTIMEOUT2 0x2B
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#define REG_PREAMBLE_MSB 0x2C
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#define REG_PREAMBLE_LSB 0x2D
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#define REG_SYNC_CONFIG 0x2E
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#define REG_SYNCVALUE1 0x2F
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#define REG_SYNCVALUE2 0x30
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#define REG_SYNCVALUE3 0x31
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#define REG_SYNCVALUE4 0x32
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#define REG_SYNCVALUE5 0x33
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#define REG_SYNCVALUE6 0x34
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#define REG_SYNCVALUE7 0x35
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#define REG_SYNCVALUE8 0x36
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#define REG_PACKETCONFIG1 0x37
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#define REG_PAYLOAD_LENGTH 0x38
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#define REG_NODEADRS 0x39
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#define REG_BROADCASTADRS 0x3A
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#define REG_AUTOMODES 0x3B
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#define REG_FIFO_THRESH 0x3C
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#define REG_PACKETCONFIG2 0x3D
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#define REG_AESKEY1 0x3E
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#define REG_AESKEY2 0x3F
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#define REG_AESKEY3 0x40
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#define REG_AESKEY4 0x41
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#define REG_AESKEY5 0x42
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#define REG_AESKEY6 0x43
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#define REG_AESKEY7 0x44
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#define REG_AESKEY8 0x45
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#define REG_AESKEY9 0x46
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#define REG_AESKEY10 0x47
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#define REG_AESKEY11 0x48
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#define REG_AESKEY12 0x49
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#define REG_AESKEY13 0x4A
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#define REG_AESKEY14 0x4B
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#define REG_AESKEY15 0x4C
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#define REG_AESKEY16 0x4D
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#define REG_TEMP1 0x4E
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#define REG_TEMP2 0x4F
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#define REG_TESTPA1 0x5A /* only present on RFM69HW */
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#define REG_TESTPA2 0x5C /* only present on RFM69HW */
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#define REG_TESTDAGC 0x6F
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/******************************************************/
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/* RF69/SX1231 bit definition */
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/******************************************************/
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/* write bit */
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#define WRITE_BIT 0x80
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/* RegOpMode */
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#define MASK_OPMODE_SEQUENCER_OFF 0x80
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#define MASK_OPMODE_LISTEN_ON 0x40
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#define MASK_OPMODE_LISTEN_ABORT 0x20
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#define MASK_OPMODE_MODE 0x1C
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#define OPMODE_MODE_SLEEP 0x00
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#define OPMODE_MODE_STANDBY 0x04 /* default */
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#define OPMODE_MODE_SYNTHESIZER 0x08
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#define OPMODE_MODE_TRANSMIT 0x0C
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#define OPMODE_MODE_RECEIVE 0x10
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/* RegDataModul */
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#define MASK_DATAMODUL_MODE 0x06
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#define MASK_DATAMODUL_MODULATION_TYPE 0x18
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#define MASK_DATAMODUL_MODULATION_SHAPE 0x03
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#define DATAMODUL_MODE_PACKET 0x00 /* default */
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#define DATAMODUL_MODE_CONTINUOUS 0x40
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#define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60
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#define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */
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#define DATAMODUL_MODULATION_TYPE_OOK 0x08
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#define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */
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#define DATAMODUL_MODULATION_SHAPE_1_0 0x01
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#define DATAMODUL_MODULATION_SHAPE_0_5 0x02
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#define DATAMODUL_MODULATION_SHAPE_0_3 0x03
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#define DATAMODUL_MODULATION_SHAPE_BR 0x01
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#define DATAMODUL_MODULATION_SHAPE_2BR 0x02
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/* RegFDevMsb (0x05)*/
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#define FDEVMASB_MASK 0x3f
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/*
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* // RegOsc1
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* #define OSC1_RCCAL_START 0x80
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* #define OSC1_RCCAL_DONE 0x40
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*
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* // RegLowBat
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* #define LOWBAT_MONITOR 0x10
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* #define LOWBAT_ON 0x08
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* #define LOWBAT_OFF 0x00 // Default
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*
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* #define LOWBAT_TRIM_1695 0x00
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* #define LOWBAT_TRIM_1764 0x01
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* #define LOWBAT_TRIM_1835 0x02 // Default
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* #define LOWBAT_TRIM_1905 0x03
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* #define LOWBAT_TRIM_1976 0x04
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* #define LOWBAT_TRIM_2045 0x05
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* #define LOWBAT_TRIM_2116 0x06
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* #define LOWBAT_TRIM_2185 0x07
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*
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*
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* // RegListen1
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* #define LISTEN1_RESOL_64 0x50
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* #define LISTEN1_RESOL_4100 0xA0 // Default
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* #define LISTEN1_RESOL_262000 0xF0
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*
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* #define LISTEN1_CRITERIA_RSSI 0x00 // Default
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* #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08
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*
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* #define LISTEN1_END_00 0x00
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* #define LISTEN1_END_01 0x02 // Default
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* #define LISTEN1_END_10 0x04
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*
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*
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* // RegListen2
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* #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default
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*
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* // RegListen3
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* #define LISTEN3_COEFRX_VALUE 0x20 // Default
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*/
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// RegPaLevel
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#define MASK_PALEVEL_PA0 0x80
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#define MASK_PALEVEL_PA1 0x40
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#define MASK_PALEVEL_PA2 0x20
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#define MASK_PALEVEL_OUTPUT_POWER 0x1F
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// RegPaRamp
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#define PARAMP_3400 0x00
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#define PARAMP_2000 0x01
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#define PARAMP_1000 0x02
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#define PARAMP_500 0x03
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#define PARAMP_250 0x04
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#define PARAMP_125 0x05
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#define PARAMP_100 0x06
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#define PARAMP_62 0x07
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#define PARAMP_50 0x08
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#define PARAMP_40 0x09 /* default */
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#define PARAMP_31 0x0A
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#define PARAMP_25 0x0B
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#define PARAMP_20 0x0C
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#define PARAMP_15 0x0D
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#define PARAMP_12 0x0E
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#define PARAMP_10 0x0F
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#define MASK_PARAMP 0x0F
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/*
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* // RegOcp
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* #define OCP_OFF 0x0F
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* #define OCP_ON 0x1A // Default
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*
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* #define OCP_TRIM_45 0x00
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* #define OCP_TRIM_50 0x01
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* #define OCP_TRIM_55 0x02
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* #define OCP_TRIM_60 0x03
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* #define OCP_TRIM_65 0x04
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* #define OCP_TRIM_70 0x05
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* #define OCP_TRIM_75 0x06
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* #define OCP_TRIM_80 0x07
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* #define OCP_TRIM_85 0x08
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* #define OCP_TRIM_90 0x09
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* #define OCP_TRIM_95 0x0A
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* #define OCP_TRIM_100 0x0B // Default
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* #define OCP_TRIM_105 0x0C
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* #define OCP_TRIM_110 0x0D
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* #define OCP_TRIM_115 0x0E
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* #define OCP_TRIM_120 0x0F
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*/
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/* RegLna (0x18) */
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#define MASK_LNA_ZIN 0x80
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#define MASK_LNA_CURRENT_GAIN 0x38
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#define MASK_LNA_GAIN 0x07
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#define LNA_GAIN_AUTO 0x00 /* default */
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#define LNA_GAIN_MAX 0x01
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#define LNA_GAIN_MAX_MINUS_6 0x02
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#define LNA_GAIN_MAX_MINUS_12 0x03
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#define LNA_GAIN_MAX_MINUS_24 0x04
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#define LNA_GAIN_MAX_MINUS_36 0x05
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#define LNA_GAIN_MAX_MINUS_48 0x06
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/* RegRxBw (0x19) and RegAfcBw (0x1A) */
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#define MASK_BW_DCC_FREQ 0xE0
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#define MASK_BW_MANTISSE 0x18
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#define MASK_BW_EXPONENT 0x07
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#define BW_DCC_16_PERCENT 0x00
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#define BW_DCC_8_PERCENT 0x20
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#define BW_DCC_4_PERCENT 0x40 /* default */
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#define BW_DCC_2_PERCENT 0x60
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#define BW_DCC_1_PERCENT 0x80
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#define BW_DCC_0_5_PERCENT 0xA0
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#define BW_DCC_0_25_PERCENT 0xC0
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#define BW_DCC_0_125_PERCENT 0xE0
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#define BW_MANT_16 0x00
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#define BW_MANT_20 0x08
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#define BW_MANT_24 0x10 /* default */
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/* RegOokPeak (0x1B) */
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#define MASK_OOKPEAK_THRESTYPE 0xc0
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#define MASK_OOKPEAK_THRESSTEP 0x38
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#define MASK_OOKPEAK_THRESDEC 0x07
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#define OOKPEAK_THRESHTYPE_FIXED 0x00
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#define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */
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#define OOKPEAK_THRESHTYPE_AVERAGE 0x80
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#define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */
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#define OOKPEAK_THRESHSTEP_1_0_DB 0x08
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#define OOKPEAK_THRESHSTEP_1_5_DB 0x10
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#define OOKPEAK_THRESHSTEP_2_0_DB 0x18
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#define OOKPEAK_THRESHSTEP_3_0_DB 0x20
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#define OOKPEAK_THRESHSTEP_4_0_DB 0x28
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#define OOKPEAK_THRESHSTEP_5_0_DB 0x30
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#define OOKPEAK_THRESHSTEP_6_0_DB 0x38
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#define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */
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#define OOKPEAK_THRESHDEC_EVERY_2ND 0x01
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#define OOKPEAK_THRESHDEC_EVERY_4TH 0x02
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#define OOKPEAK_THRESHDEC_EVERY_8TH 0x03
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#define OOKPEAK_THRESHDEC_TWICE 0x04
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#define OOKPEAK_THRESHDEC_4_TIMES 0x05
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#define OOKPEAK_THRESHDEC_8_TIMES 0x06
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#define OOKPEAK_THRESHDEC_16_TIMES 0x07
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/*
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* // RegOokAvg
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* #define OOKAVG_AVERAGETHRESHFILT_00 0x00
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* #define OOKAVG_AVERAGETHRESHFILT_01 0x40
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* #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default
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* #define OOKAVG_AVERAGETHRESHFILT_11 0xC0
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*
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*
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* // RegAfcFei
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* #define AFCFEI_FEI_DONE 0x40
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* #define AFCFEI_FEI_START 0x20
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* #define AFCFEI_AFC_DONE 0x10
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* #define AFCFEI_AFCAUTOCLEAR_ON 0x08
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* #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
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*
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* #define AFCFEI_AFCAUTO_ON 0x04
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* #define AFCFEI_AFCAUTO_OFF 0x00 // Default
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*
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* #define AFCFEI_AFC_CLEAR 0x02
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* #define AFCFEI_AFC_START 0x01
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*
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* // RegRssiConfig
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* #define RSSI_FASTRX_ON 0x08
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* #define RSSI_FASTRX_OFF 0x00 // Default
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* #define RSSI_DONE 0x02
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* #define RSSI_START 0x01
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*/
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/* RegDioMapping1 */
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#define MASK_DIO0 0xC0
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#define MASK_DIO1 0x30
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#define MASK_DIO2 0x0C
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#define MASK_DIO3 0x03
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#define SHIFT_DIO0 6
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#define SHIFT_DIO1 4
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#define SHIFT_DIO2 2
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#define SHIFT_DIO3 0
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/* RegDioMapping2 */
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#define MASK_DIO4 0xC0
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#define MASK_DIO5 0x30
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#define SHIFT_DIO4 6
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#define SHIFT_DIO5 4
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/* DIO numbers */
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#define DIO0 0
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#define DIO1 1
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#define DIO2 2
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#define DIO3 3
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#define DIO4 4
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#define DIO5 5
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/* DIO Mapping values (packet mode) */
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#define DIO_MODE_READY_DIO4 0x00
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#define DIO_MODE_READY_DIO5 0x03
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#define DIO_CLK_OUT 0x00
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#define DIO_DATA 0x01
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#define DIO_TIMEOUT_DIO1 0x03
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#define DIO_TIMEOUT_DIO4 0x00
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#define DIO_RSSI_DIO0 0x03
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#define DIO_RSSI_DIO3_4 0x01
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#define DIO_RX_READY 0x02
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#define DIO_PLL_LOCK 0x03
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#define DIO_TX_READY 0x01
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#define DIO_FIFO_FULL_DIO1 0x01
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#define DIO_FIFO_FULL_DIO3 0x00
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#define DIO_SYNC_ADDRESS 0x02
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#define DIO_FIFO_NOT_EMPTY_DIO1 0x02
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#define DIO_FIFO_NOT_EMPTY_FIO2 0x00
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#define DIO_AUTOMODE 0x04
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#define DIO_FIFO_LEVEL 0x00
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#define DIO_CRC_OK 0x00
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#define DIO_PAYLOAD_READY 0x01
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#define DIO_PACKET_SENT 0x00
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#define DIO_DCLK 0x00
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/* RegDioMapping2 CLK_OUT part */
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#define MASK_DIOMAPPING2_CLK_OUT 0x07
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#define DIOMAPPING2_CLK_OUT_NO_DIV 0x00
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#define DIOMAPPING2_CLK_OUT_DIV_2 0x01
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#define DIOMAPPING2_CLK_OUT_DIV_4 0x02
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#define DIOMAPPING2_CLK_OUT_DIV_8 0x03
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#define DIOMAPPING2_CLK_OUT_DIV_16 0x04
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#define DIOMAPPING2_CLK_OUT_DIV_32 0x05
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#define DIOMAPPING2_CLK_OUT_RC 0x06
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#define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */
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/* RegIrqFlags1 */
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#define MASK_IRQFLAGS1_MODE_READY 0x80
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#define MASK_IRQFLAGS1_RX_READY 0x40
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#define MASK_IRQFLAGS1_TX_READY 0x20
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#define MASK_IRQFLAGS1_PLL_LOCK 0x10
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#define MASK_IRQFLAGS1_RSSI 0x08
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#define MASK_IRQFLAGS1_TIMEOUT 0x04
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#define MASK_IRQFLAGS1_AUTOMODE 0x02
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#define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01
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/* RegIrqFlags2 */
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#define MASK_IRQFLAGS2_FIFO_FULL 0x80
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#define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40
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#define MASK_IRQFLAGS2_FIFO_LEVEL 0x20
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#define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10
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#define MASK_IRQFLAGS2_PACKET_SENT 0x08
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#define MASK_IRQFLAGS2_PAYLOAD_READY 0x04
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#define MASK_IRQFLAGS2_CRC_OK 0x02
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#define MASK_IRQFLAGS2_LOW_BAT 0x01
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/* RegSyncConfig */
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#define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */
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#define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40
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#define MASK_SYNC_CONFIG_SYNC_SIZE 0x38
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#define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07
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/* RegPacketConfig1 */
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#define MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE 0x80
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#define MASK_PACKETCONFIG1_DCFREE 0x60
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#define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */
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#define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08
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#define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06
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#define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */
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#define PACKETCONFIG1_DCFREE_MANCHESTER 0x20
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#define PACKETCONFIG1_DCFREE_WHITENING 0x40
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#define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */
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#define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02
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#define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04
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/*
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* // RegAutoModes
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* #define AUTOMODES_ENTER_OFF 0x00 // Default
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* #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20
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* #define AUTOMODES_ENTER_FIFOLEVEL 0x40
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* #define AUTOMODES_ENTER_CRCOK 0x60
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* #define AUTOMODES_ENTER_PAYLOADREADY 0x80
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* #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0
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* #define AUTOMODES_ENTER_PACKETSENT 0xC0
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* #define AUTOMODES_ENTER_FIFOEMPTY 0xE0
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*
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* #define AUTOMODES_EXIT_OFF 0x00 // Default
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* #define AUTOMODES_EXIT_FIFOEMPTY 0x04
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* #define AUTOMODES_EXIT_FIFOLEVEL 0x08
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* #define AUTOMODES_EXIT_CRCOK 0x0C
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* #define AUTOMODES_EXIT_PAYLOADREADY 0x10
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* #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14
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* #define AUTOMODES_EXIT_PACKETSENT 0x18
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* #define AUTOMODES_EXIT_RXTIMEOUT 0x1C
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*
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* #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default
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* #define AUTOMODES_INTERMEDIATE_STANDBY 0x01
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* #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02
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* #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03
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*
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*/
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/* RegFifoThresh (0x3c) */
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#define MASK_FIFO_THRESH_TXSTART 0x80
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#define MASK_FIFO_THRESH_VALUE 0x7F
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/*
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*
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* // RegPacketConfig2
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* #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default
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* #define PACKET2_RXRESTARTDELAY_2BITS 0x10
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* #define PACKET2_RXRESTARTDELAY_4BITS 0x20
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* #define PACKET2_RXRESTARTDELAY_8BITS 0x30
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* #define PACKET2_RXRESTARTDELAY_16BITS 0x40
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* #define PACKET2_RXRESTARTDELAY_32BITS 0x50
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* #define PACKET2_RXRESTARTDELAY_64BITS 0x60
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* #define PACKET2_RXRESTARTDELAY_128BITS 0x70
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* #define PACKET2_RXRESTARTDELAY_256BITS 0x80
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* #define PACKET2_RXRESTARTDELAY_512BITS 0x90
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* #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0
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* #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0
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* #define PACKET2_RXRESTARTDELAY_NONE 0xC0
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* #define PACKET2_RXRESTART 0x04
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*
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* #define PACKET2_AUTORXRESTART_ON 0x02 // Default
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* #define PACKET2_AUTORXRESTART_OFF 0x00
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*
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* #define PACKET2_AES_ON 0x01
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* #define PACKET2_AES_OFF 0x00 // Default
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*
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*
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* // RegTemp1
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* #define TEMP1_MEAS_START 0x08
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* #define TEMP1_MEAS_RUNNING 0x04
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* #define TEMP1_ADCLOWPOWER_ON 0x01 // Default
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* #define TEMP1_ADCLOWPOWER_OFF 0x00
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*/
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// RegTestDagc (0x6F)
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#define DAGC_NORMAL 0x00 /* Reset value */
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#define DAGC_IMPROVED_LOWBETA1 0x20
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#define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */
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