// SPDX-License-Identifier: GPL-2.0+
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/*
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* FB driver for the uPD161704 LCD Controller
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*
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* Copyright (C) 2014 Seong-Woo Kim
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*
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* Based on fb_ili9325.c by Noralf Tronnes
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* Based on ili9325.c by Jeroen Domburg
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* Init code from UTFT library by Henning Karlsen
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include "fbtft.h"
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#define DRVNAME "fb_upd161704"
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#define WIDTH 240
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#define HEIGHT 320
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#define BPP 16
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static int init_display(struct fbtft_par *par)
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{
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par->fbtftops.reset(par);
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/* Initialization sequence from Lib_UTFT */
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/* register reset */
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write_reg(par, 0x0003, 0x0001); /* Soft reset */
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/* oscillator start */
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write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */
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udelay(100);
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/* y-setting */
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write_reg(par, 0x0024, 0x007B); /* amplitude setting */
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udelay(10);
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write_reg(par, 0x0025, 0x003B); /* amplitude setting */
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write_reg(par, 0x0026, 0x0034); /* amplitude setting */
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udelay(10);
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write_reg(par, 0x0027, 0x0004); /* amplitude setting */
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write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */
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udelay(10);
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write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */
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write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */
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udelay(10);
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write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */
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write_reg(par, 0x0063, 0x0022); /* adjustment V34 positive polarity */
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udelay(10);
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write_reg(par, 0x0064, 0x0027); /* adjustment V31 negative polarity */
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udelay(10);
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write_reg(par, 0x0065, 0x0014); /* adjustment V61 negative polarity */
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udelay(10);
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write_reg(par, 0x0066, 0x0010); /* adjustment V61 negative polarity */
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/* Basical clock for 1 line (BASECOUNT[7:0]) number specified */
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write_reg(par, 0x002E, 0x002D);
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/* Power supply setting */
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write_reg(par, 0x0019, 0x0000); /* DC/DC output setting */
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udelay(200);
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write_reg(par, 0x001A, 0x1000); /* DC/DC frequency setting */
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write_reg(par, 0x001B, 0x0023); /* DC/DC rising setting */
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write_reg(par, 0x001C, 0x0C01); /* Regulator voltage setting */
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write_reg(par, 0x001D, 0x0000); /* Regulator current setting */
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write_reg(par, 0x001E, 0x0009); /* VCOM output setting */
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write_reg(par, 0x001F, 0x0035); /* VCOM amplitude setting */
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write_reg(par, 0x0020, 0x0015); /* VCOMM cencter setting */
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write_reg(par, 0x0018, 0x1E7B); /* DC/DC operation setting */
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/* windows setting */
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write_reg(par, 0x0008, 0x0000); /* Minimum X address */
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write_reg(par, 0x0009, 0x00EF); /* Maximum X address */
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write_reg(par, 0x000a, 0x0000); /* Minimum Y address */
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write_reg(par, 0x000b, 0x013F); /* Maximum Y address */
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/* LCD display area setting */
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write_reg(par, 0x0029, 0x0000); /* [LCDSIZE] X MIN. size set */
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write_reg(par, 0x002A, 0x0000); /* [LCDSIZE] Y MIN. size set */
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write_reg(par, 0x002B, 0x00EF); /* [LCDSIZE] X MAX. size set */
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write_reg(par, 0x002C, 0x013F); /* [LCDSIZE] Y MAX. size set */
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/* Gate scan setting */
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write_reg(par, 0x0032, 0x0002);
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/* n line inversion line number */
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write_reg(par, 0x0033, 0x0000);
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/* Line inversion/frame inversion/interlace setting */
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write_reg(par, 0x0037, 0x0000);
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/* Gate scan operation setting register */
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write_reg(par, 0x003B, 0x0001);
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/* Color mode */
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/*GS = 0: 260-k color (64 gray scale), GS = 1: 8 color (2 gray scale) */
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write_reg(par, 0x0004, 0x0000);
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/* RAM control register */
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write_reg(par, 0x0005, 0x0000); /*Window access 00:Normal, 10:Window */
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/* Display setting register 2 */
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write_reg(par, 0x0001, 0x0000);
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/* display setting */
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write_reg(par, 0x0000, 0x0000); /* display on */
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return 0;
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}
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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switch (par->info->var.rotate) {
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/* R20h = Horizontal GRAM Start Address */
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/* R21h = Vertical GRAM Start Address */
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case 0:
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write_reg(par, 0x0006, xs);
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write_reg(par, 0x0007, ys);
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break;
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case 180:
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write_reg(par, 0x0006, WIDTH - 1 - xs);
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write_reg(par, 0x0007, HEIGHT - 1 - ys);
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break;
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case 270:
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write_reg(par, 0x0006, WIDTH - 1 - ys);
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write_reg(par, 0x0007, xs);
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break;
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case 90:
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write_reg(par, 0x0006, ys);
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write_reg(par, 0x0007, HEIGHT - 1 - xs);
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break;
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}
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write_reg(par, 0x0e); /* Write Data to GRAM */
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}
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static int set_var(struct fbtft_par *par)
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{
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switch (par->info->var.rotate) {
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/* AM: GRAM update direction */
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case 0:
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write_reg(par, 0x01, 0x0000);
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write_reg(par, 0x05, 0x0000);
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break;
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case 180:
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write_reg(par, 0x01, 0x00C0);
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write_reg(par, 0x05, 0x0000);
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break;
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case 270:
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write_reg(par, 0x01, 0x0080);
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write_reg(par, 0x05, 0x0001);
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break;
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case 90:
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write_reg(par, 0x01, 0x0040);
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write_reg(par, 0x05, 0x0001);
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break;
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}
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return 0;
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}
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static struct fbtft_display display = {
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.regwidth = 16,
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.width = WIDTH,
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.height = HEIGHT,
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.fbtftops = {
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.init_display = init_display,
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.set_addr_win = set_addr_win,
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.set_var = set_var,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:upd161704");
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MODULE_ALIAS("platform:upd161704");
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MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
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MODULE_AUTHOR("Seong-Woo Kim");
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MODULE_LICENSE("GPL");
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