// SPDX-License-Identifier: GPL-2.0+
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/*
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* FB driver for the HX8340BN LCD Controller
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*
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* This display uses 9-bit SPI: Data/Command bit + 8 data bits
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* For platforms that doesn't support 9-bit, the driver is capable
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* of emulating this using 8-bit transfer.
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* This is done by transferring eight 9-bit words in 9 bytes.
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*
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* Copyright (C) 2013 Noralf Tronnes
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/vmalloc.h>
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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#include <video/mipi_display.h>
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#include "fbtft.h"
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#define DRVNAME "fb_hx8340bn"
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#define WIDTH 176
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#define HEIGHT 220
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#define TXBUFLEN (4 * PAGE_SIZE)
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#define DEFAULT_GAMMA "1 3 0E 5 0 2 09 0 6 1 7 1 0 2 2\n" \
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"3 3 17 8 4 7 05 7 6 0 3 1 6 0 0 "
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static bool emulate;
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module_param(emulate, bool, 0000);
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MODULE_PARM_DESC(emulate, "Force emulation in 9-bit mode");
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static int init_display(struct fbtft_par *par)
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{
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par->fbtftops.reset(par);
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/* BTL221722-276L startup sequence, from datasheet */
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/*
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* SETEXTCOM: Set extended command set (C1h)
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* This command is used to set extended command set access enable.
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* Enable: After command (C1h), must write: ffh,83h,40h
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*/
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write_reg(par, 0xC1, 0xFF, 0x83, 0x40);
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/*
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* Sleep out
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* This command turns off sleep mode.
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* In this mode the DC/DC converter is enabled, Internal oscillator
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* is started, and panel scanning is started.
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*/
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write_reg(par, 0x11);
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mdelay(150);
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/* Undoc'd register? */
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write_reg(par, 0xCA, 0x70, 0x00, 0xD9);
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/*
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* SETOSC: Set Internal Oscillator (B0h)
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* This command is used to set internal oscillator related settings
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* OSC_EN: Enable internal oscillator
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* Internal oscillator frequency: 125% x 2.52MHz
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*/
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write_reg(par, 0xB0, 0x01, 0x11);
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/* Drive ability setting */
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write_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06);
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mdelay(20);
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/*
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* SETPWCTR5: Set Power Control 5(B5h)
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* This command is used to set VCOM Low and VCOM High Voltage
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* VCOMH 0110101 : 3.925
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* VCOML 0100000 : -1.700
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* 45h=69 VCOMH: "VMH" + 5d VCOML: "VMH" + 5d
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*/
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write_reg(par, 0xB5, 0x35, 0x20, 0x45);
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/*
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* SETPWCTR4: Set Power Control 4(B4h)
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* VRH[4:0]: Specify the VREG1 voltage adjusting.
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* VREG1 voltage is for gamma voltage setting.
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* BT[2:0]: Switch the output factor of step-up circuit 2
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* for VGH and VGL voltage generation.
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*/
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write_reg(par, 0xB4, 0x33, 0x25, 0x4C);
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mdelay(10);
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/*
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* Interface Pixel Format (3Ah)
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* This command is used to define the format of RGB picture data,
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* which is to be transfer via the system and RGB interface.
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* RGB interface: 16 Bit/Pixel
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*/
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write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
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/*
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* Display on (29h)
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* This command is used to recover from DISPLAY OFF mode.
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* Output from the Frame Memory is enabled.
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*/
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write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
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mdelay(10);
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return 0;
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}
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, 0x00, xs, 0x00, xe);
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write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, 0x00, ys, 0x00, ye);
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write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
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}
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static int set_var(struct fbtft_par *par)
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{
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/* MADCTL - Memory data access control */
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/* RGB/BGR can be set with H/W pin SRGB and MADCTL BGR bit */
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#define MY BIT(7)
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#define MX BIT(6)
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#define MV BIT(5)
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switch (par->info->var.rotate) {
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case 0:
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, par->bgr << 3);
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break;
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case 270:
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
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MX | MV | (par->bgr << 3));
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break;
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case 180:
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
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MX | MY | (par->bgr << 3));
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break;
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case 90:
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
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MY | MV | (par->bgr << 3));
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break;
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}
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return 0;
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}
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/*
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* Gamma Curve selection, GC (only GC0 can be customized):
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* 0 = 2.2, 1 = 1.8, 2 = 2.5, 3 = 1.0
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* Gamma string format:
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* OP0 OP1 CP0 CP1 CP2 CP3 CP4 MP0 MP1 MP2 MP3 MP4 MP5 CGM0 CGM1
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* ON0 ON1 CN0 CN1 CN2 CN3 CN4 MN0 MN1 MN2 MN3 MN4 MN5 XXXX GC
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*/
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#define CURVE(num, idx) curves[(num) * par->gamma.num_values + (idx)]
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static int set_gamma(struct fbtft_par *par, u32 *curves)
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{
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static const unsigned long mask[] = {
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0x0f, 0x0f, 0x1f, 0x0f, 0x0f, 0x0f, 0x1f, 0x07, 0x07, 0x07,
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0x07, 0x07, 0x07, 0x03, 0x03, 0x0f, 0x0f, 0x1f, 0x0f, 0x0f,
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0x0f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00,
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};
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int i, j;
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/* apply mask */
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for (i = 0; i < par->gamma.num_curves; i++)
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for (j = 0; j < par->gamma.num_values; j++)
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CURVE(i, j) &= mask[i * par->gamma.num_values + j];
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/* Gamma Set (26h) */
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write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 1 << CURVE(1, 14));
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if (CURVE(1, 14))
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return 0; /* only GC0 can be customized */
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write_reg(par, 0xC2,
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(CURVE(0, 8) << 4) | CURVE(0, 7),
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(CURVE(0, 10) << 4) | CURVE(0, 9),
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(CURVE(0, 12) << 4) | CURVE(0, 11),
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CURVE(0, 2),
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(CURVE(0, 4) << 4) | CURVE(0, 3),
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CURVE(0, 5),
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CURVE(0, 6),
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(CURVE(0, 1) << 4) | CURVE(0, 0),
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(CURVE(0, 14) << 2) | CURVE(0, 13));
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write_reg(par, 0xC3,
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(CURVE(1, 8) << 4) | CURVE(1, 7),
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(CURVE(1, 10) << 4) | CURVE(1, 9),
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(CURVE(1, 12) << 4) | CURVE(1, 11),
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CURVE(1, 2),
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(CURVE(1, 4) << 4) | CURVE(1, 3),
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CURVE(1, 5),
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CURVE(1, 6),
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(CURVE(1, 1) << 4) | CURVE(1, 0));
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mdelay(10);
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return 0;
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}
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#undef CURVE
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static struct fbtft_display display = {
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.regwidth = 8,
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.width = WIDTH,
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.height = HEIGHT,
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.txbuflen = TXBUFLEN,
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.gamma_num = 2,
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.gamma_len = 15,
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.gamma = DEFAULT_GAMMA,
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.fbtftops = {
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.init_display = init_display,
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.set_addr_win = set_addr_win,
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.set_var = set_var,
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.set_gamma = set_gamma,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8340bn", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:hx8340bn");
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MODULE_ALIAS("platform:hx8340bn");
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MODULE_DESCRIPTION("FB driver for the HX8340BN LCD Controller");
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MODULE_AUTHOR("Noralf Tronnes");
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MODULE_LICENSE("GPL");
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