// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2018 Macronix International Co., Ltd.
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//
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// Authors:
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// Mason Yang <masonccyang@mxic.com.tw>
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// zhengxunli <zhengxunli@mxic.com.tw>
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// Boris Brezillon <boris.brezillon@bootlin.com>
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//
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#define HC_CFG 0x0
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#define HC_CFG_IF_CFG(x) ((x) << 27)
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#define HC_CFG_DUAL_SLAVE BIT(31)
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#define HC_CFG_INDIVIDUAL BIT(30)
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#define HC_CFG_NIO(x) (((x) / 4) << 27)
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#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
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#define HC_CFG_TYPE_SPI_NOR 0
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#define HC_CFG_TYPE_SPI_NAND 1
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#define HC_CFG_TYPE_SPI_RAM 2
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#define HC_CFG_TYPE_RAW_NAND 3
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#define HC_CFG_SLV_ACT(x) ((x) << 21)
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#define HC_CFG_CLK_PH_EN BIT(20)
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#define HC_CFG_CLK_POL_INV BIT(19)
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#define HC_CFG_BIG_ENDIAN BIT(18)
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#define HC_CFG_DATA_PASS BIT(17)
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#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
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#define HC_CFG_MAN_START_EN BIT(3)
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#define HC_CFG_MAN_START BIT(2)
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#define HC_CFG_MAN_CS_EN BIT(1)
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#define HC_CFG_MAN_CS_ASSERT BIT(0)
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#define INT_STS 0x4
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#define INT_STS_EN 0x8
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#define INT_SIG_EN 0xc
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#define INT_STS_ALL GENMASK(31, 0)
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#define INT_RDY_PIN BIT(26)
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#define INT_RDY_SR BIT(25)
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#define INT_LNR_SUSP BIT(24)
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#define INT_ECC_ERR BIT(17)
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#define INT_CRC_ERR BIT(16)
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#define INT_LWR_DIS BIT(12)
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#define INT_LRD_DIS BIT(11)
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#define INT_SDMA_INT BIT(10)
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#define INT_DMA_FINISH BIT(9)
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#define INT_RX_NOT_FULL BIT(3)
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#define INT_RX_NOT_EMPTY BIT(2)
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#define INT_TX_NOT_FULL BIT(1)
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#define INT_TX_EMPTY BIT(0)
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#define HC_EN 0x10
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#define HC_EN_BIT BIT(0)
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#define TXD(x) (0x14 + ((x) * 4))
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#define RXD 0x24
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#define SS_CTRL(s) (0x30 + ((s) * 4))
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#define LRD_CFG 0x44
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#define LWR_CFG 0x80
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#define RWW_CFG 0x70
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#define OP_READ BIT(23)
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#define OP_DUMMY_CYC(x) ((x) << 17)
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#define OP_ADDR_BYTES(x) ((x) << 14)
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#define OP_CMD_BYTES(x) (((x) - 1) << 13)
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#define OP_OCTA_CRC_EN BIT(12)
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#define OP_DQS_EN BIT(11)
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#define OP_ENHC_EN BIT(10)
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#define OP_PREAMBLE_EN BIT(9)
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#define OP_DATA_DDR BIT(8)
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#define OP_DATA_BUSW(x) ((x) << 6)
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#define OP_ADDR_DDR BIT(5)
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#define OP_ADDR_BUSW(x) ((x) << 3)
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#define OP_CMD_DDR BIT(2)
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#define OP_CMD_BUSW(x) (x)
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#define OP_BUSW_1 0
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#define OP_BUSW_2 1
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#define OP_BUSW_4 2
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#define OP_BUSW_8 3
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#define OCTA_CRC 0x38
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#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
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#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
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#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
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#define ONFI_DIN_CNT(s) (0x3c + (s))
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#define LRD_CTRL 0x48
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#define RWW_CTRL 0x74
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#define LWR_CTRL 0x84
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#define LMODE_EN BIT(31)
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#define LMODE_SLV_ACT(x) ((x) << 21)
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#define LMODE_CMD1(x) ((x) << 8)
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#define LMODE_CMD0(x) (x)
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#define LRD_ADDR 0x4c
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#define LWR_ADDR 0x88
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#define LRD_RANGE 0x50
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#define LWR_RANGE 0x8c
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#define AXI_SLV_ADDR 0x54
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#define DMAC_RD_CFG 0x58
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#define DMAC_WR_CFG 0x94
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#define DMAC_CFG_PERIPH_EN BIT(31)
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#define DMAC_CFG_ALLFLUSH_EN BIT(30)
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#define DMAC_CFG_LASTFLUSH_EN BIT(29)
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#define DMAC_CFG_QE(x) (((x) + 1) << 16)
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#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
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#define DMAC_CFG_BURST_SZ(x) ((x) << 8)
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#define DMAC_CFG_DIR_READ BIT(1)
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#define DMAC_CFG_START BIT(0)
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#define DMAC_RD_CNT 0x5c
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#define DMAC_WR_CNT 0x98
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#define SDMA_ADDR 0x60
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#define DMAM_CFG 0x64
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#define DMAM_CFG_START BIT(31)
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#define DMAM_CFG_CONT BIT(30)
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#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
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#define DMAM_CFG_DIR_READ BIT(1)
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#define DMAM_CFG_EN BIT(0)
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#define DMAM_CNT 0x68
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#define LNR_TIMER_TH 0x6c
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#define RDM_CFG0 0x78
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#define RDM_CFG0_POLY(x) (x)
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#define RDM_CFG1 0x7c
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#define RDM_CFG1_RDM_EN BIT(31)
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#define RDM_CFG1_SEED(x) (x)
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#define LWR_SUSP_CTRL 0x90
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#define LWR_SUSP_CTRL_EN BIT(31)
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#define DMAS_CTRL 0x9c
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#define DMAS_CTRL_EN BIT(31)
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#define DMAS_CTRL_DIR_READ BIT(30)
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#define DATA_STROB 0xa0
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#define DATA_STROB_EDO_EN BIT(2)
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#define DATA_STROB_INV_POL BIT(1)
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#define DATA_STROB_DELAY_2CYC BIT(0)
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#define IDLY_CODE(x) (0xa4 + ((x) * 4))
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#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
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#define GPIO 0xc4
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#define GPIO_PT(x) BIT(3 + ((x) * 16))
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#define GPIO_RESET(x) BIT(2 + ((x) * 16))
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#define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
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#define GPIO_WPB(x) BIT((x) * 16)
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#define HC_VER 0xd0
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#define HW_TEST(x) (0xe0 + ((x) * 4))
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struct mxic_spi {
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struct clk *ps_clk;
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struct clk *send_clk;
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struct clk *send_dly_clk;
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void __iomem *regs;
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u32 cur_speed_hz;
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};
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static int mxic_spi_clk_enable(struct mxic_spi *mxic)
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{
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int ret;
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ret = clk_prepare_enable(mxic->send_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(mxic->send_dly_clk);
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if (ret)
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goto err_send_dly_clk;
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return ret;
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err_send_dly_clk:
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clk_disable_unprepare(mxic->send_clk);
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return ret;
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}
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static void mxic_spi_clk_disable(struct mxic_spi *mxic)
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{
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clk_disable_unprepare(mxic->send_clk);
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clk_disable_unprepare(mxic->send_dly_clk);
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}
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static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
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{
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writel(IDLY_CODE_VAL(0, idly_code) |
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IDLY_CODE_VAL(1, idly_code) |
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IDLY_CODE_VAL(2, idly_code) |
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IDLY_CODE_VAL(3, idly_code),
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mxic->regs + IDLY_CODE(0));
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writel(IDLY_CODE_VAL(4, idly_code) |
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IDLY_CODE_VAL(5, idly_code) |
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IDLY_CODE_VAL(6, idly_code) |
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IDLY_CODE_VAL(7, idly_code),
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mxic->regs + IDLY_CODE(1));
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}
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static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
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{
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int ret;
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ret = clk_set_rate(mxic->send_clk, freq);
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if (ret)
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return ret;
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ret = clk_set_rate(mxic->send_dly_clk, freq);
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if (ret)
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return ret;
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/*
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* A constant delay range from 0x0 ~ 0x1F for input delay,
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* the unit is 78 ps, the max input delay is 2.418 ns.
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*/
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mxic_spi_set_input_delay_dqs(mxic, 0xf);
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/*
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* Phase degree = 360 * freq * output-delay
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* where output-delay is a constant value 1 ns in FPGA.
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*
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* Get Phase degree = 360 * freq * 1 ns
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* = 360 * freq * 1 sec / 1000000000
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* = 9 * freq / 25000000
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*/
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ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
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if (ret)
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return ret;
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return 0;
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}
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static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
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{
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int ret;
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if (mxic->cur_speed_hz == freq)
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return 0;
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mxic_spi_clk_disable(mxic);
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ret = mxic_spi_clk_setup(mxic, freq);
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if (ret)
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return ret;
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ret = mxic_spi_clk_enable(mxic);
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if (ret)
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return ret;
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mxic->cur_speed_hz = freq;
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return 0;
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}
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static void mxic_spi_hw_init(struct mxic_spi *mxic)
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{
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writel(0, mxic->regs + DATA_STROB);
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writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
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writel(0, mxic->regs + HC_EN);
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writel(0, mxic->regs + LRD_CFG);
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writel(0, mxic->regs + LRD_CTRL);
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writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
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HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
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mxic->regs + HC_CFG);
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}
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static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
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void *rxbuf, unsigned int len)
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{
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unsigned int pos = 0;
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while (pos < len) {
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unsigned int nbytes = len - pos;
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u32 data = 0xffffffff;
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u32 sts;
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int ret;
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if (nbytes > 4)
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nbytes = 4;
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if (txbuf)
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memcpy(&data, txbuf + pos, nbytes);
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ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
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sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
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if (ret)
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return ret;
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writel(data, mxic->regs + TXD(nbytes % 4));
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ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
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sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
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if (ret)
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return ret;
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ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
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sts & INT_RX_NOT_EMPTY, 0,
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USEC_PER_SEC);
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if (ret)
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return ret;
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data = readl(mxic->regs + RXD);
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if (rxbuf) {
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data >>= (8 * (4 - nbytes));
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memcpy(rxbuf + pos, &data, nbytes);
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}
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WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
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pos += nbytes;
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}
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return 0;
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}
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static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
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op->dummy.buswidth > 4 || op->cmd.buswidth > 4)
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return false;
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if (op->data.nbytes && op->dummy.nbytes &&
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op->data.buswidth != op->dummy.buswidth)
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return false;
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if (op->addr.nbytes > 7)
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return false;
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return spi_mem_default_supports_op(mem, op);
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}
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static int mxic_spi_mem_exec_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
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int nio = 1, i, ret;
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u32 ss_ctrl;
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u8 addr[8];
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u8 opcode = op->cmd.opcode;
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ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
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if (ret)
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return ret;
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if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
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nio = 4;
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else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
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nio = 2;
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writel(HC_CFG_NIO(nio) |
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HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
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HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
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HC_CFG_MAN_CS_EN,
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mxic->regs + HC_CFG);
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writel(HC_EN_BIT, mxic->regs + HC_EN);
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ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
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if (op->addr.nbytes)
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ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
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OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
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if (op->dummy.nbytes)
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ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
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if (op->data.nbytes) {
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ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
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if (op->data.dir == SPI_MEM_DATA_IN)
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ss_ctrl |= OP_READ;
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}
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writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
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writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
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mxic->regs + HC_CFG);
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ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
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if (ret)
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goto out;
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for (i = 0; i < op->addr.nbytes; i++)
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addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
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ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
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if (ret)
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goto out;
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ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
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if (ret)
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goto out;
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ret = mxic_spi_data_xfer(mxic,
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op->data.dir == SPI_MEM_DATA_OUT ?
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op->data.buf.out : NULL,
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op->data.dir == SPI_MEM_DATA_IN ?
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op->data.buf.in : NULL,
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op->data.nbytes);
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out:
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writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
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mxic->regs + HC_CFG);
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writel(0, mxic->regs + HC_EN);
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return ret;
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}
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static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
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.supports_op = mxic_spi_mem_supports_op,
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.exec_op = mxic_spi_mem_exec_op,
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};
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static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
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{
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struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
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if (!lvl) {
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writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
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mxic->regs + HC_CFG);
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writel(HC_EN_BIT, mxic->regs + HC_EN);
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writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
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mxic->regs + HC_CFG);
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} else {
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writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
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mxic->regs + HC_CFG);
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writel(0, mxic->regs + HC_EN);
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}
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}
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static int mxic_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mxic_spi *mxic = spi_master_get_devdata(master);
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unsigned int busw = OP_BUSW_1;
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int ret;
|
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if (t->rx_buf && t->tx_buf) {
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if (((spi->mode & SPI_TX_QUAD) &&
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!(spi->mode & SPI_RX_QUAD)) ||
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((spi->mode & SPI_TX_DUAL) &&
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!(spi->mode & SPI_RX_DUAL)))
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return -ENOTSUPP;
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}
|
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ret = mxic_spi_set_freq(mxic, t->speed_hz);
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if (ret)
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return ret;
|
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if (t->tx_buf) {
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if (spi->mode & SPI_TX_QUAD)
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busw = OP_BUSW_4;
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else if (spi->mode & SPI_TX_DUAL)
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busw = OP_BUSW_2;
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} else if (t->rx_buf) {
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if (spi->mode & SPI_RX_QUAD)
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busw = OP_BUSW_4;
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else if (spi->mode & SPI_RX_DUAL)
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busw = OP_BUSW_2;
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}
|
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writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
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OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0),
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mxic->regs + SS_CTRL(0));
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ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
|
if (ret)
|
return ret;
|
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spi_finalize_current_transfer(master);
|
|
return 0;
|
}
|
|
static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
|
{
|
struct spi_master *master = dev_get_drvdata(dev);
|
struct mxic_spi *mxic = spi_master_get_devdata(master);
|
|
mxic_spi_clk_disable(mxic);
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clk_disable_unprepare(mxic->ps_clk);
|
|
return 0;
|
}
|
|
static int __maybe_unused mxic_spi_runtime_resume(struct device *dev)
|
{
|
struct spi_master *master = dev_get_drvdata(dev);
|
struct mxic_spi *mxic = spi_master_get_devdata(master);
|
int ret;
|
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ret = clk_prepare_enable(mxic->ps_clk);
|
if (ret) {
|
dev_err(dev, "Cannot enable ps_clock.\n");
|
return ret;
|
}
|
|
return mxic_spi_clk_enable(mxic);
|
}
|
|
static const struct dev_pm_ops mxic_spi_dev_pm_ops = {
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SET_RUNTIME_PM_OPS(mxic_spi_runtime_suspend,
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mxic_spi_runtime_resume, NULL)
|
};
|
|
static int mxic_spi_probe(struct platform_device *pdev)
|
{
|
struct spi_master *master;
|
struct resource *res;
|
struct mxic_spi *mxic;
|
int ret;
|
|
master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
|
if (!master)
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, master);
|
|
mxic = spi_master_get_devdata(master);
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
|
if (IS_ERR(mxic->ps_clk))
|
return PTR_ERR(mxic->ps_clk);
|
|
mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
|
if (IS_ERR(mxic->send_clk))
|
return PTR_ERR(mxic->send_clk);
|
|
mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
|
if (IS_ERR(mxic->send_dly_clk))
|
return PTR_ERR(mxic->send_dly_clk);
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
|
mxic->regs = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR(mxic->regs))
|
return PTR_ERR(mxic->regs);
|
|
pm_runtime_enable(&pdev->dev);
|
master->auto_runtime_pm = true;
|
|
master->num_chipselect = 1;
|
master->mem_ops = &mxic_spi_mem_ops;
|
|
master->set_cs = mxic_spi_set_cs;
|
master->transfer_one = mxic_spi_transfer_one;
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
master->mode_bits = SPI_CPOL | SPI_CPHA |
|
SPI_RX_DUAL | SPI_TX_DUAL |
|
SPI_RX_QUAD | SPI_TX_QUAD;
|
|
mxic_spi_hw_init(mxic);
|
|
ret = spi_register_master(master);
|
if (ret) {
|
dev_err(&pdev->dev, "spi_register_master failed\n");
|
pm_runtime_disable(&pdev->dev);
|
}
|
|
return ret;
|
}
|
|
static int mxic_spi_remove(struct platform_device *pdev)
|
{
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
pm_runtime_disable(&pdev->dev);
|
spi_unregister_master(master);
|
|
return 0;
|
}
|
|
static const struct of_device_id mxic_spi_of_ids[] = {
|
{ .compatible = "mxicy,mx25f0a-spi", },
|
{ /* sentinel */ }
|
};
|
MODULE_DEVICE_TABLE(of, mxic_spi_of_ids);
|
|
static struct platform_driver mxic_spi_driver = {
|
.probe = mxic_spi_probe,
|
.remove = mxic_spi_remove,
|
.driver = {
|
.name = "mxic-spi",
|
.of_match_table = mxic_spi_of_ids,
|
.pm = &mxic_spi_dev_pm_ops,
|
},
|
};
|
module_platform_driver(mxic_spi_driver);
|
|
MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
|
MODULE_DESCRIPTION("MX25F0A SPI controller driver");
|
MODULE_LICENSE("GPL v2");
|
