/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Freescale SPI controller driver.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright (C) 2006 Polycom, Inc.
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* GRLIB support:
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* Copyright (c) 2012 Aeroflex Gaisler AB.
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* Author: Andreas Larsson <andreas@gaisler.com>
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*/
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#ifndef __SPI_FSL_SPI_H__
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#define __SPI_FSL_SPI_H__
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/* SPI Controller registers */
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struct fsl_spi_reg {
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__be32 cap; /* TYPE_GRLIB specific */
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u8 res1[0x1C];
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__be32 mode;
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__be32 event;
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__be32 mask;
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__be32 command;
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__be32 transmit;
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__be32 receive;
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__be32 slvsel; /* TYPE_GRLIB specific */
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};
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/* SPI Controller mode register definitions */
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#define SPMODE_LOOP (1 << 30)
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#define SPMODE_CI_INACTIVEHIGH (1 << 29)
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#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
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#define SPMODE_DIV16 (1 << 27)
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#define SPMODE_REV (1 << 26)
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#define SPMODE_MS (1 << 25)
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#define SPMODE_ENABLE (1 << 24)
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#define SPMODE_LEN(x) ((x) << 20)
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#define SPMODE_PM(x) ((x) << 16)
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#define SPMODE_OP (1 << 14)
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#define SPMODE_CG(x) ((x) << 7)
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/* TYPE_GRLIB SPI Controller capability register definitions */
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#define SPCAP_SSEN(x) (((x) >> 16) & 0x1)
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#define SPCAP_SSSZ(x) (((x) >> 24) & 0xff)
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#define SPCAP_MAXWLEN(x) (((x) >> 20) & 0xf)
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/*
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* Default for SPI Mode:
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* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
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*/
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#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
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SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
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/* SPIE register values */
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#define SPIE_NE 0x00000200 /* Not empty */
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#define SPIE_NF 0x00000100 /* Not full */
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/* SPIM register values */
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#define SPIM_NE 0x00000200 /* Not empty */
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#define SPIM_NF 0x00000100 /* Not full */
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#endif /* __SPI_FSL_SPI_H__ */
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