/* SPDX-License-Identifier: GPL-2.0 */
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/************************************************************************/
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/* */
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/* dc395x.h */
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/* */
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/* Device Driver for Tekram DC395(U/UW/F), DC315(U) */
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/* PCI SCSI Bus Master Host Adapter */
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/* (SCSI chip set used Tekram ASIC TRM-S1040) */
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/* */
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/************************************************************************/
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#ifndef DC395x_H
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#define DC395x_H
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/************************************************************************/
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/* */
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/* Initial values */
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/* */
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/************************************************************************/
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#define DC395x_MAX_CMD_QUEUE 32
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/* #define DC395x_MAX_QTAGS 32 */
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#define DC395x_MAX_QTAGS 16
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#define DC395x_MAX_SCSI_ID 16
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#define DC395x_MAX_CMD_PER_LUN DC395x_MAX_QTAGS
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#define DC395x_MAX_SG_TABLESIZE 64 /* HW limitation */
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#define DC395x_MAX_SG_LISTENTRY 64 /* Must be equal or lower to previous */
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/* item */
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#define DC395x_MAX_SRB_CNT 63
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/* #define DC395x_MAX_CAN_QUEUE 7 * DC395x_MAX_QTAGS */
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#define DC395x_MAX_CAN_QUEUE DC395x_MAX_SRB_CNT
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#define DC395x_END_SCAN 2
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#define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
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#define DC395x_MAX_RETRIES 3
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#if 0
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#define SYNC_FIRST
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#endif
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#define NORM_REC_LVL 0
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/************************************************************************/
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/* */
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/* Various definitions */
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/* */
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/************************************************************************/
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#define BIT31 0x80000000
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#define BIT30 0x40000000
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#define BIT29 0x20000000
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#define BIT28 0x10000000
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#define BIT27 0x08000000
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#define BIT26 0x04000000
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#define BIT25 0x02000000
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#define BIT24 0x01000000
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#define BIT23 0x00800000
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#define BIT22 0x00400000
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#define BIT21 0x00200000
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#define BIT20 0x00100000
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#define BIT19 0x00080000
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#define BIT18 0x00040000
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#define BIT17 0x00020000
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#define BIT16 0x00010000
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#define BIT15 0x00008000
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#define BIT14 0x00004000
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#define BIT13 0x00002000
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#define BIT12 0x00001000
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#define BIT11 0x00000800
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#define BIT10 0x00000400
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#define BIT9 0x00000200
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#define BIT8 0x00000100
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#define BIT7 0x00000080
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#define BIT6 0x00000040
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#define BIT5 0x00000020
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#define BIT4 0x00000010
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#define BIT3 0x00000008
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#define BIT2 0x00000004
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#define BIT1 0x00000002
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#define BIT0 0x00000001
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/* UnitCtrlFlag */
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#define UNIT_ALLOCATED BIT0
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#define UNIT_INFO_CHANGED BIT1
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#define FORMATING_MEDIA BIT2
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#define UNIT_RETRY BIT3
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/* UnitFlags */
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#define DASD_SUPPORT BIT0
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#define SCSI_SUPPORT BIT1
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#define ASPI_SUPPORT BIT2
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/* SRBState machine definition */
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#define SRB_FREE 0x0000
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#define SRB_WAIT 0x0001
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#define SRB_READY 0x0002
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#define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */
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#define SRB_MSGIN 0x0008
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#define SRB_EXTEND_MSGIN 0x0010
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#define SRB_COMMAND 0x0020
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#define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */
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#define SRB_DISCONNECT 0x0080
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#define SRB_DATA_XFER 0x0100
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#define SRB_XFERPAD 0x0200
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#define SRB_STATUS 0x0400
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#define SRB_COMPLETED 0x0800
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#define SRB_ABORT_SENT 0x1000
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#define SRB_DO_SYNC_NEGO 0x2000
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#define SRB_DO_WIDE_NEGO 0x4000
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#define SRB_UNEXPECT_RESEL 0x8000
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/************************************************************************/
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/* */
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/* ACB Config */
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/* */
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/************************************************************************/
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#define HCC_WIDE_CARD 0x20
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#define HCC_SCSI_RESET 0x10
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#define HCC_PARITY 0x08
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#define HCC_AUTOTERM 0x04
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#define HCC_LOW8TERM 0x02
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#define HCC_UP8TERM 0x01
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/* ACBFlag */
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#define RESET_DEV BIT0
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#define RESET_DETECT BIT1
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#define RESET_DONE BIT2
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/* DCBFlag */
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#define ABORT_DEV_ BIT0
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/* SRBstatus */
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#define SRB_OK BIT0
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#define ABORTION BIT1
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#define OVER_RUN BIT2
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#define UNDER_RUN BIT3
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#define PARITY_ERROR BIT4
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#define SRB_ERROR BIT5
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/* SRBFlag */
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#define DATAOUT BIT7
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#define DATAIN BIT6
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#define RESIDUAL_VALID BIT5
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#define ENABLE_TIMER BIT4
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#define RESET_DEV0 BIT2
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#define ABORT_DEV BIT1
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#define AUTO_REQSENSE BIT0
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/* Adapter status */
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#define H_STATUS_GOOD 0
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#define H_SEL_TIMEOUT 0x11
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#define H_OVER_UNDER_RUN 0x12
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#define H_UNEXP_BUS_FREE 0x13
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#define H_TARGET_PHASE_F 0x14
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#define H_INVALID_CCB_OP 0x16
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#define H_LINK_CCB_BAD 0x17
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#define H_BAD_TARGET_DIR 0x18
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#define H_DUPLICATE_CCB 0x19
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#define H_BAD_CCB_OR_SG 0x1A
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#define H_ABORT 0x0FF
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/* SCSI BUS Status byte codes */
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#define SCSI_STAT_GOOD 0x0 /* Good status */
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#define SCSI_STAT_CHECKCOND 0x02 /* SCSI Check Condition */
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#define SCSI_STAT_CONDMET 0x04 /* Condition Met */
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#define SCSI_STAT_BUSY 0x08 /* Target busy status */
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#define SCSI_STAT_INTER 0x10 /* Intermediate status */
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#define SCSI_STAT_INTERCONDMET 0x14 /* Intermediate condition met */
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#define SCSI_STAT_RESCONFLICT 0x18 /* Reservation conflict */
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#define SCSI_STAT_CMDTERM 0x22 /* Command Terminated */
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#define SCSI_STAT_QUEUEFULL 0x28 /* Queue Full */
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#define SCSI_STAT_UNEXP_BUS_F 0xFD /* Unexpect Bus Free */
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#define SCSI_STAT_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */
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#define SCSI_STAT_SEL_TIMEOUT 0xFF /* Selection Time out */
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/* Sync_Mode */
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#define SYNC_WIDE_TAG_ATNT_DISABLE 0
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#define SYNC_NEGO_ENABLE BIT0
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#define SYNC_NEGO_DONE BIT1
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#define WIDE_NEGO_ENABLE BIT2
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#define WIDE_NEGO_DONE BIT3
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#define WIDE_NEGO_STATE BIT4
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#define EN_TAG_QUEUEING BIT5
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#define EN_ATN_STOP BIT6
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#define SYNC_NEGO_OFFSET 15
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/* SCSI MSG BYTE */
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#define MSG_COMPLETE 0x00
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#define MSG_EXTENDED 0x01
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#define MSG_SAVE_PTR 0x02
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#define MSG_RESTORE_PTR 0x03
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#define MSG_DISCONNECT 0x04
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#define MSG_INITIATOR_ERROR 0x05
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#define MSG_ABORT 0x06
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#define MSG_REJECT_ 0x07
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#define MSG_NOP 0x08
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#define MSG_PARITY_ERROR 0x09
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#define MSG_LINK_CMD_COMPL 0x0A
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#define MSG_LINK_CMD_COMPL_FLG 0x0B
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#define MSG_BUS_RESET 0x0C
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#define MSG_ABORT_TAG 0x0D
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#define MSG_SIMPLE_QTAG 0x20
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#define MSG_HEAD_QTAG 0x21
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#define MSG_ORDER_QTAG 0x22
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#define MSG_IGNOREWIDE 0x23
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#define MSG_IDENTIFY 0x80
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#define MSG_HOST_ID 0xC0
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/* SCSI STATUS BYTE */
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#define STATUS_GOOD 0x00
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#define CHECK_CONDITION_ 0x02
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#define STATUS_BUSY 0x08
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#define STATUS_INTERMEDIATE 0x10
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#define RESERVE_CONFLICT 0x18
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/* cmd->result */
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#define STATUS_MASK_ 0xFF
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#define MSG_MASK 0xFF00
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#define RETURN_MASK 0xFF0000
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/************************************************************************/
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/* */
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/* Inquiry Data format */
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/* */
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/************************************************************************/
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struct ScsiInqData
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{ /* INQ */
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u8 DevType; /* Periph Qualifier & Periph Dev Type */
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u8 RMB_TypeMod; /* rem media bit & Dev Type Modifier */
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u8 Vers; /* ISO, ECMA, & ANSI versions */
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u8 RDF; /* AEN, TRMIOP, & response data format */
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u8 AddLen; /* length of additional data */
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u8 Res1; /* reserved */
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u8 Res2; /* reserved */
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u8 Flags; /* RelADr, Wbus32, Wbus16, Sync, etc. */
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u8 VendorID[8]; /* Vendor Identification */
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u8 ProductID[16]; /* Product Identification */
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u8 ProductRev[4]; /* Product Revision */
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};
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/* Inquiry byte 0 masks */
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#define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
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#define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
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/* Inquiry byte 1 mask */
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#define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
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/* Peripheral Device Type definitions */
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/* See include/scsi/scsi.h */
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#define TYPE_NODEV SCSI_DEVTYPE /* Unknown or no device type */
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#ifndef TYPE_PRINTER /* */
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# define TYPE_PRINTER 0x02 /* Printer device */
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#endif /* */
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#ifndef TYPE_COMM /* */
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# define TYPE_COMM 0x09 /* Communications device */
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#endif
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/************************************************************************/
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/* */
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/* Inquiry flag definitions (Inq data byte 7) */
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/* */
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/************************************************************************/
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#define SCSI_INQ_RELADR 0x80 /* device supports relative addressing */
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#define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
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#define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
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#define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
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#define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
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#define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
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#define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
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#define ENABLE_CE 1
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#define DISABLE_CE 0
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#define EEPROM_READ 0x80
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/************************************************************************/
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/* */
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/* The PCI configuration register offset for TRM_S1040 */
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/* */
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/************************************************************************/
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#define TRM_S1040_ID 0x00 /* Vendor and Device ID */
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#define TRM_S1040_COMMAND 0x04 /* PCI command register */
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#define TRM_S1040_IOBASE 0x10 /* I/O Space base address */
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#define TRM_S1040_ROMBASE 0x30 /* Expansion ROM Base Address */
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#define TRM_S1040_INTLINE 0x3C /* Interrupt line */
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/************************************************************************/
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/* */
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/* The SCSI register offset for TRM_S1040 */
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/* */
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/************************************************************************/
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#define TRM_S1040_SCSI_STATUS 0x80 /* SCSI Status (R) */
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#define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
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#define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
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#define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
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#define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
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#define COMMANDABORT 0x0040 /* SCSI command abort */
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#define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
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#define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
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#define PARITYERROR 0x0008 /* SCSI parity error */
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#define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
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#define PH_DATA_OUT 0x00 /* Data out phase */
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#define PH_DATA_IN 0x01 /* Data in phase */
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#define PH_COMMAND 0x02 /* Command phase */
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#define PH_STATUS 0x03 /* Status phase */
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#define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */
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#define PH_MSG_OUT 0x06 /* Message out phase */
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#define PH_MSG_IN 0x07 /* Message in phase */
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#define TRM_S1040_SCSI_CONTROL 0x80 /* SCSI Control (W) */
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#define DO_CLRATN 0x0400 /* Clear ATN */
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#define DO_SETATN 0x0200 /* Set ATN */
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#define DO_CMDABORT 0x0100 /* Abort SCSI command */
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#define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
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#define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
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#define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
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#define DO_DATALATCH 0x0002 /* Enable SCSI bus data input (latched) */
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/* #define DO_DATALATCH 0x0000 */ /* KG: DISable SCSI bus data latch */
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#define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
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#define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
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#define TRM_S1040_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
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#define TRM_S1040_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
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#define INT_SCAM 0x80 /* SCAM selection interrupt */
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#define INT_SELECT 0x40 /* Selection interrupt */
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#define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
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#define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
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#define INT_RESELECTED 0x08 /* Reselected interrupt */
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#define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */
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#define INT_BUSSERVICE 0x02 /* Bus service interrupt */
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#define INT_CMDDONE 0x01 /* SCSI command done interrupt */
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#define TRM_S1040_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
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/************************************************************************/
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/* */
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/* Bit Name Definition */
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/* --------- ------------- ---------------------------- */
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/* 07-05 0 RSVD Reversed. Always 0. */
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/* 04 0 OFFSET4 Reversed for LVDS. Always 0. */
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/* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */
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/* */
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/************************************************************************/
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#define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */
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#define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
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#define WIDE_SYNC 0x10 /* Enable WIDE synchronous */
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#define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
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/************************************************************************/
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/* */
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/* SYNCM 7 6 5 4 3 2 1 0 */
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/* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 */
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/* Default 0 0 0 0 0 0 0 0 */
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/* */
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/* Bit Name Definition */
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/* --------- ------------- --------------------------- */
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/* 07-06 0 RSVD Reversed. Always read 0 */
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/* 05 0 LVDS Reversed. Always read 0 */
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/* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI */
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/* transfer. */
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/* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. */
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/* */
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/* @@ When this bit is set, */
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/* the synchronous period bits 2:0 */
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/* in the Synchronous Mode register */
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/* are used to transfer data */
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/* at the Fast-20 rate. */
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/* @@ When this bit is unset, */
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/* the synchronous period bits 2:0 */
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/* in the Synchronous Mode Register */
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/* are used to transfer data */
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/* at the Fast-10 rate (or Fast-40 w/ LVDS). */
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/* */
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/* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
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/* SXPD[02:00] These 3 bits specify */
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/* the Synchronous SCSI Transfer */
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/* Rate for Fast-20 and Fast-10. */
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/* These bits are also reset */
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/* by a SCSI Bus reset. */
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/* */
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/* For Fast-10 bit ALTPD = 0 and LVDS = 0 */
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/* and bit2,bit1,bit0 is defined as follows : */
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/* */
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/* 000 100ns, 10.0 MHz */
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/* 001 150ns, 6.6 MHz */
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/* 010 200ns, 5.0 MHz */
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/* 011 250ns, 4.0 MHz */
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/* 100 300ns, 3.3 MHz */
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/* 101 350ns, 2.8 MHz */
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/* 110 400ns, 2.5 MHz */
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/* 111 450ns, 2.2 MHz */
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/* */
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/* For Fast-20 bit ALTPD = 1 and LVDS = 0 */
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/* and bit2,bit1,bit0 is defined as follows : */
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/* */
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/* 000 50ns, 20.0 MHz */
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/* 001 75ns, 13.3 MHz */
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/* 010 100ns, 10.0 MHz */
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/* 011 125ns, 8.0 MHz */
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/* 100 150ns, 6.6 MHz */
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/* 101 175ns, 5.7 MHz */
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/* 110 200ns, 5.0 MHz */
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/* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */
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/* */
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/* For Fast-40 bit ALTPD = 0 and LVDS = 1 */
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/* and bit2,bit1,bit0 is defined as follows : */
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/* */
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/* 000 25ns, 40.0 MHz */
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/* 001 50ns, 20.0 MHz */
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/* 010 75ns, 13.3 MHz */
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/* 011 100ns, 10.0 MHz */
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/* 100 125ns, 8.0 MHz */
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/* 101 150ns, 6.6 MHz */
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/* 110 175ns, 5.7 MHz */
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/* 111 200ns, 5.0 MHz */
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/* */
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/************************************************************************/
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#define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
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#define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
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#define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
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#define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
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#define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
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#define EN_SCAM 0x80 /* Enable SCAM selection interrupt */
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#define EN_SELECT 0x40 /* Enable selection interrupt */
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#define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */
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#define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */
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#define EN_RESELECTED 0x08 /* Enable reselected interrupt */
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#define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt */
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#define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */
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#define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */
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#define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
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#define PHASELATCH 0x40 /* Enable phase latch */
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#define INITIATOR 0x20 /* Enable initiator mode */
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#define PARITYCHECK 0x10 /* Enable parity check */
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#define BLOCKRST 0x01 /* Disable SCSI reset1 */
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#define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
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#define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
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#define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
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#define FAST_FILTER 0x04 /* ? */
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#define ACTIVE_NEG 0x02 /* Enable active negation */
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#define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */
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#define CFG2_WIDEFIFO 0x02 /* */
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#define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
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#define SCMD_COMP 0x12 /* Command complete */
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#define SCMD_SEL_ATN 0x60 /* Selection with ATN */
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#define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
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#define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
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#define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
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#define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
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#define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
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#define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
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#define SCMD_MSGACCEPT 0xD8 /* Message accept */
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/************************************************************************/
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/* */
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/* Code Command Description */
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/* ---- ---------------------------------------- */
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/* 02 Enable reselection with FIFO */
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/* 40 Select without ATN with FIFO */
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/* 60 Select with ATN with FIFO */
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/* 64 Select with ATN3 with FIFO */
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/* A0 Select with ATN and stop with FIFO */
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/* C0 Transfer information out with FIFO */
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/* C1 Transfer information out with DMA */
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/* C2 Transfer information in with FIFO */
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/* C3 Transfer information in with DMA */
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/* 12 Initiator command complete with FIFO */
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/* 50 Initiator transfer information out sequence without ATN */
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/* with FIFO */
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/* 70 Initiator transfer information out sequence with ATN */
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/* with FIFO */
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/* 74 Initiator transfer information out sequence with ATN3 */
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/* with FIFO */
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/* 52 Initiator transfer information in sequence without ATN */
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/* with FIFO */
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/* 72 Initiator transfer information in sequence with ATN */
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/* with FIFO */
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/* 76 Initiator transfer information in sequence with ATN3 */
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/* with FIFO */
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/* 90 Initiator transfer information out command complete */
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/* with FIFO */
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/* 92 Initiator transfer information in command complete */
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/* with FIFO */
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/* D2 Enable selection */
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/* 08 Reselection */
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/* 48 Disconnect command with FIFO */
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/* 88 Terminate command with FIFO */
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/* C8 Target command complete with FIFO */
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/* 18 SCAM Arbitration/ Selection */
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/* 5A Enable reselection */
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/* 98 Select without ATN with FIFO */
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/* B8 Select with ATN with FIFO */
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/* D8 Message Accepted */
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/* 58 NOP */
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/* */
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/************************************************************************/
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#define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
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#define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
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#define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
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#define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
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#define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */
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#define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */
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#define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */
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#define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
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#define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
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#define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
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#define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
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#define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
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#define TCR0_OFFSET_MASK 0x001F /* Offset number */
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#define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
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#define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
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#define NON_TAG_BUSY 0x0080 /* Non tag command active */
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#define ACTTAG_MASK 0x007F /* Active tags */
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/************************************************************************/
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/* */
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/* The DMA register offset for TRM_S1040 */
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/* */
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/************************************************************************/
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#define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
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#define DMACMD_SG 0x02 /* Enable HW S/G support */
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#define DMACMD_DIR 0x01 /* 1 = read from SCSI write to Host */
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#define XFERDATAIN_SG 0x0103 /* Transfer data in w/ SG */
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#define XFERDATAOUT_SG 0x0102 /* Transfer data out w/ SG */
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#define XFERDATAIN 0x0101 /* Transfer data in w/o SG */
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#define XFERDATAOUT 0x0100 /* Transfer data out w/o SG */
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#define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
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#define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */
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#define DMARESETMODULE 0x10 /* Reset PCI/DMA module */
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#define STOPDMAXFER 0x08 /* Stop DMA transfer */
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#define ABORTXFER 0x04 /* Abort DMA transfer */
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#define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
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#define STARTDMAXFER 0x01 /* Start DMA transfer */
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#define TRM_S1040_DMA_FIFOSTAT 0xA2 /* DMA FIFO Status (R) */
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#define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
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#define XFERPENDING 0x80 /* Transfer pending */
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#define SCSIBUSY 0x40 /* SCSI busy */
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#define GLOBALINT 0x20 /* DMA_INTEN bit 0-4 set */
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#define FORCEDMACOMP 0x10 /* Force DMA transfer complete */
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#define DMAXFERERROR 0x08 /* DMA transfer error */
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#define DMAXFERABORT 0x04 /* DMA transfer abort */
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#define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
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#define SCSICOMP 0x01 /* SCSI complete interrupt */
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#define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */
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#define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */
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#define EN_DMAXFERERROR 0x08 /* DMA transfer error */
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#define EN_DMAXFERABORT 0x04 /* DMA transfer abort */
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#define EN_DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
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#define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
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#define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
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#define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature (SG?) */
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#define DMA_PCI_DUAL_ADDR 0x4000 /* */
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#define DMA_CFG_RES 0x2000 /* Always 1 */
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#define DMA_AUTO_CLR_FIFO 0x1000 /* DISable DMA auto clear FIFO */
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#define DMA_MEM_MULTI_READ 0x0800 /* */
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#define DMA_MEM_WRITE_INVAL 0x0400 /* Memory write and invalidate */
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#define DMA_FIFO_CTRL 0x0300 /* Control FIFO operation with DMA */
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#define DMA_FIFO_HALF_HALF 0x0200 /* Keep half filled on both read/write */
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#define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W), 24bits */
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#define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
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#define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
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#define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */
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/************************************************************************/
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/* */
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/* The general register offset for TRM_S1040 */
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/* */
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/************************************************************************/
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#define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */
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#define CTRL_LED 0x80 /* Control onboard LED */
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#define EN_EEPROM 0x10 /* Enable EEPROM programming */
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#define DIS_TERM 0x08 /* Disable onboard termination */
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#define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
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#define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
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#define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
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#define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */
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#define GTIMEOUT 0x80 /* Global timer reach 0 */
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#define EXT68HIGH 0x40 /* Higher 8 bit connected externally */
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#define INT68HIGH 0x20 /* Higher 8 bit connected internally */
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#define CON5068 0x10 /* External 50/68 pin connected (low) */
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#define CON68 0x08 /* Internal 68 pin connected (low) */
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#define CON50 0x04 /* Internal 50 pin connected (low!) */
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#define WIDESCSI 0x02 /* Wide SCSI card */
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#define STATUS_LOAD_DEFAULT 0x01 /* */
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#define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
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#define NVR_BITOUT 0x08 /* Serial data out */
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#define NVR_BITIN 0x04 /* Serial data in */
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#define NVR_CLOCK 0x02 /* Serial clock */
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#define NVR_SELECT 0x01 /* Serial select */
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#define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */
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#define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */
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#define TRM_S1040_GEN_TIMER 0xDB /* Global timer */
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/************************************************************************/
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/* */
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/* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */
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/* */
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/************************************************************************/
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#define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
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#define NTC_DO_TAG_QUEUEING 0x10 /* Enable SCSI tag queuing */
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#define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */
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#define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
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#define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
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#define NTC_DO_PARITY_CHK 0x01 /* (it should define at NAC) */
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/* Parity check enable */
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/************************************************************************/
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/* */
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/* Nvram Initiater bits definition */
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/* */
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/************************************************************************/
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#if 0
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#define MORE2_DRV BIT0
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#define GREATER_1G BIT1
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#define RST_SCSI_BUS BIT2
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#define ACTIVE_NEGATION BIT3
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#define NO_SEEK BIT4
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#define LUN_CHECK BIT5
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#endif
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/************************************************************************/
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/* */
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/* Nvram Adapter Cfg bits definition */
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/* */
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/************************************************************************/
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#define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */
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#define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
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#define NAC_GREATER_1G 0x02 /* > 1G support enable */
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#define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */
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/* #define NAC_DO_PARITY_CHK 0x08 */ /* Parity check enable */
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#endif
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