/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Intel Core SoC Power Management Controller Header File
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*
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* Copyright (c) 2016, Intel Corporation.
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* All Rights Reserved.
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*
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* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
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* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
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*/
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#ifndef PMC_CORE_H
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#define PMC_CORE_H
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#include <linux/bits.h>
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#define PMC_BASE_ADDR_DEFAULT 0xFE000000
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/* Sunrise Point Power Management Controller PCI Device ID */
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#define SPT_PMC_PCI_DEVICE_ID 0x9d21
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#define SPT_PMC_BASE_ADDR_OFFSET 0x48
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#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
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#define SPT_PMC_PM_CFG_OFFSET 0x18
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#define SPT_PMC_PM_STS_OFFSET 0x1c
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#define SPT_PMC_MTPMC_OFFSET 0x20
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#define SPT_PMC_MFPMC_OFFSET 0x38
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#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
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#define SPT_PMC_VRIC1_OFFSET 0x31c
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#define SPT_PMC_MPHY_CORE_STS_0 0x1143
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#define SPT_PMC_MPHY_CORE_STS_1 0x1142
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#define SPT_PMC_MPHY_COM_STS_0 0x1155
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#define SPT_PMC_MMIO_REG_LEN 0x1000
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#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68
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#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
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#define MTPMC_MASK 0xffff0000
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#define PPFEAR_MAX_NUM_ENTRIES 12
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#define SPT_PPFEAR_NUM_ENTRIES 5
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#define SPT_PMC_READ_DISABLE_BIT 0x16
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#define SPT_PMC_MSG_FULL_STS_BIT 0x18
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#define NUM_RETRIES 100
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#define SPT_NUM_IP_IGN_ALLOWED 17
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#define SPT_PMC_LTR_CUR_PLT 0x350
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#define SPT_PMC_LTR_CUR_ASLT 0x354
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#define SPT_PMC_LTR_SPA 0x360
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#define SPT_PMC_LTR_SPB 0x364
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#define SPT_PMC_LTR_SATA 0x368
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#define SPT_PMC_LTR_GBE 0x36C
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#define SPT_PMC_LTR_XHCI 0x370
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#define SPT_PMC_LTR_RESERVED 0x374
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#define SPT_PMC_LTR_ME 0x378
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#define SPT_PMC_LTR_EVA 0x37C
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#define SPT_PMC_LTR_SPC 0x380
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#define SPT_PMC_LTR_AZ 0x384
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#define SPT_PMC_LTR_LPSS 0x38C
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#define SPT_PMC_LTR_CAM 0x390
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#define SPT_PMC_LTR_SPD 0x394
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#define SPT_PMC_LTR_SPE 0x398
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#define SPT_PMC_LTR_ESPI 0x39C
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#define SPT_PMC_LTR_SCC 0x3A0
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#define SPT_PMC_LTR_ISH 0x3A4
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/* Sunrise Point: PGD PFET Enable Ack Status Registers */
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enum ppfear_regs {
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SPT_PMC_XRAM_PPFEAR0A = 0x590,
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SPT_PMC_XRAM_PPFEAR0B,
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SPT_PMC_XRAM_PPFEAR0C,
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SPT_PMC_XRAM_PPFEAR0D,
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SPT_PMC_XRAM_PPFEAR1A,
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};
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#define SPT_PMC_BIT_PMC BIT(0)
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#define SPT_PMC_BIT_OPI BIT(1)
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#define SPT_PMC_BIT_SPI BIT(2)
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#define SPT_PMC_BIT_XHCI BIT(3)
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#define SPT_PMC_BIT_SPA BIT(4)
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#define SPT_PMC_BIT_SPB BIT(5)
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#define SPT_PMC_BIT_SPC BIT(6)
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#define SPT_PMC_BIT_GBE BIT(7)
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#define SPT_PMC_BIT_SATA BIT(0)
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#define SPT_PMC_BIT_HDA_PGD0 BIT(1)
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#define SPT_PMC_BIT_HDA_PGD1 BIT(2)
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#define SPT_PMC_BIT_HDA_PGD2 BIT(3)
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#define SPT_PMC_BIT_HDA_PGD3 BIT(4)
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#define SPT_PMC_BIT_RSVD_0B BIT(5)
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#define SPT_PMC_BIT_LPSS BIT(6)
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#define SPT_PMC_BIT_LPC BIT(7)
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#define SPT_PMC_BIT_SMB BIT(0)
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#define SPT_PMC_BIT_ISH BIT(1)
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#define SPT_PMC_BIT_P2SB BIT(2)
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#define SPT_PMC_BIT_DFX BIT(3)
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#define SPT_PMC_BIT_SCC BIT(4)
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#define SPT_PMC_BIT_RSVD_0C BIT(5)
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#define SPT_PMC_BIT_FUSE BIT(6)
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#define SPT_PMC_BIT_CAMREA BIT(7)
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#define SPT_PMC_BIT_RSVD_0D BIT(0)
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#define SPT_PMC_BIT_USB3_OTG BIT(1)
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#define SPT_PMC_BIT_EXI BIT(2)
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#define SPT_PMC_BIT_CSE BIT(3)
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#define SPT_PMC_BIT_CSME_KVM BIT(4)
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#define SPT_PMC_BIT_CSME_PMT BIT(5)
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#define SPT_PMC_BIT_CSME_CLINK BIT(6)
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#define SPT_PMC_BIT_CSME_PTIO BIT(7)
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#define SPT_PMC_BIT_CSME_USBR BIT(0)
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#define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
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#define SPT_PMC_BIT_CSME_SMT BIT(2)
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#define SPT_PMC_BIT_RSVD_1A BIT(3)
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#define SPT_PMC_BIT_CSME_SMS2 BIT(4)
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#define SPT_PMC_BIT_CSME_SMS1 BIT(5)
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#define SPT_PMC_BIT_CSME_RTC BIT(6)
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#define SPT_PMC_BIT_CSME_PSF BIT(7)
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#define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
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#define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
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#define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
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#define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
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#define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
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#define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
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#define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
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#define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
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#define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
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#define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
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#define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
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#define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
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#define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
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#define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
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#define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
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#define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
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#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
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#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
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#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
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#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
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#define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
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#define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
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/* Cannonlake Power Management Controller register offsets */
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#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
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#define CNP_PMC_PM_CFG_OFFSET 0x1818
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#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
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#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
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/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
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#define CNP_PMC_HOST_PPFEAR0A 0x1D90
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#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
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#define CNP_PMC_MMIO_REG_LEN 0x2000
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#define CNP_PPFEAR_NUM_ENTRIES 8
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#define CNP_PMC_READ_DISABLE_BIT 22
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#define CNP_NUM_IP_IGN_ALLOWED 19
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#define CNP_PMC_LTR_CUR_PLT 0x1B50
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#define CNP_PMC_LTR_CUR_ASLT 0x1B54
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#define CNP_PMC_LTR_SPA 0x1B60
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#define CNP_PMC_LTR_SPB 0x1B64
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#define CNP_PMC_LTR_SATA 0x1B68
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#define CNP_PMC_LTR_GBE 0x1B6C
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#define CNP_PMC_LTR_XHCI 0x1B70
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#define CNP_PMC_LTR_RESERVED 0x1B74
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#define CNP_PMC_LTR_ME 0x1B78
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#define CNP_PMC_LTR_EVA 0x1B7C
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#define CNP_PMC_LTR_SPC 0x1B80
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#define CNP_PMC_LTR_AZ 0x1B84
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#define CNP_PMC_LTR_LPSS 0x1B8C
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#define CNP_PMC_LTR_CAM 0x1B90
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#define CNP_PMC_LTR_SPD 0x1B94
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#define CNP_PMC_LTR_SPE 0x1B98
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#define CNP_PMC_LTR_ESPI 0x1B9C
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#define CNP_PMC_LTR_SCC 0x1BA0
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#define CNP_PMC_LTR_ISH 0x1BA4
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#define CNP_PMC_LTR_CNV 0x1BF0
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#define CNP_PMC_LTR_EMMC 0x1BF4
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#define CNP_PMC_LTR_UFSX2 0x1BF8
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#define LTR_DECODED_VAL GENMASK(9, 0)
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#define LTR_DECODED_SCALE GENMASK(12, 10)
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#define LTR_REQ_SNOOP BIT(15)
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#define LTR_REQ_NONSNOOP BIT(31)
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#define ICL_PPFEAR_NUM_ENTRIES 9
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#define ICL_NUM_IP_IGN_ALLOWED 20
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#define ICL_PMC_LTR_WIGIG 0x1BFC
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#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64
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#define TGL_NUM_IP_IGN_ALLOWED 22
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#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A
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/*
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* Tigerlake Power Management Controller register offsets
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*/
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#define TGL_LPM_EN_OFFSET 0x1C78
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#define TGL_LPM_RESIDENCY_OFFSET 0x1C80
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/* Tigerlake Low Power Mode debug registers */
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#define TGL_LPM_STATUS_OFFSET 0x1C3C
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#define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C
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const char *tgl_lpm_modes[] = {
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"S0i2.0",
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"S0i2.1",
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"S0i2.2",
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"S0i3.0",
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"S0i3.1",
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"S0i3.2",
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"S0i3.3",
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"S0i3.4",
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NULL
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};
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struct pmc_bit_map {
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const char *name;
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u32 bit_mask;
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};
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/**
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* struct pmc_reg_map - Structure used to define parameter unique to a
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PCH family
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* @pfear_sts: Maps name of IP block to PPFEAR* bit
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* @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
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* @pll_sts: Maps name of PLL to corresponding bit status
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* @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
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* @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets
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* @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
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* @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
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* @regmap_length: Length of memory to map from PWRMBASE address to access
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* @ppfear0_offset: PWRMBASE offset to to read PPFEAR*
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* @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
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* PPFEAR
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* @pm_cfg_offset: PWRMBASE offset to PM_CFG register
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* @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
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* @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
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*
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* Each PCH has unique set of register offsets and bit indexes. This structure
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* captures them to have a common implementation.
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*/
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struct pmc_reg_map {
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const struct pmc_bit_map **pfear_sts;
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const struct pmc_bit_map *mphy_sts;
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const struct pmc_bit_map *pll_sts;
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const struct pmc_bit_map **slps0_dbg_maps;
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const struct pmc_bit_map *ltr_show_sts;
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const struct pmc_bit_map *msr_sts;
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const struct pmc_bit_map **lpm_sts;
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const u32 slp_s0_offset;
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const int slp_s0_res_counter_step;
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const u32 ltr_ignore_offset;
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const int regmap_length;
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const u32 ppfear0_offset;
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const int ppfear_buckets;
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const u32 pm_cfg_offset;
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const int pm_read_disable_bit;
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const u32 slps0_dbg_offset;
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const u32 ltr_ignore_max;
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const u32 pm_vric1_offset;
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/* Low Power Mode registers */
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const char **lpm_modes;
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const u32 lpm_en_offset;
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const u32 lpm_residency_offset;
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const u32 lpm_status_offset;
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const u32 lpm_live_status_offset;
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};
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/**
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* struct pmc_dev - pmc device structure
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* @base_addr: contains pmc base address
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* @regbase: pointer to io-remapped memory location
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* @map: pointer to pmc_reg_map struct that contains platform
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* specific attributes
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* @dbgfs_dir: path to debugfs interface
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* @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
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* used to read MPHY PG and PLL status are available
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* @mutex_lock: mutex to complete one transcation
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* @check_counters: On resume, check if counters are getting incremented
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* @pc10_counter: PC10 residency counter
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* @s0ix_counter: S0ix residency (step adjusted)
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*
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* pmc_dev contains info about power management controller device.
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*/
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struct pmc_dev {
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u32 base_addr;
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void __iomem *regbase;
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const struct pmc_reg_map *map;
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struct dentry *dbgfs_dir;
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int pmc_xram_read_bit;
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struct mutex lock; /* generic mutex lock for PMC Core */
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bool check_counters; /* Check for counter increments on resume */
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u64 pc10_counter;
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u64 s0ix_counter;
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};
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#endif /* PMC_CORE_H */
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