// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Core SoC Power Management Controller Driver
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*
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* Copyright (c) 2016, Intel Corporation.
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* All Rights Reserved.
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*
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* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
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* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/acpi.h>
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#include <linux/bitfield.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/suspend.h>
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#include <linux/uaccess.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/msr.h>
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#include <asm/tsc.h>
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#include "intel_pmc_core.h"
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static struct pmc_dev pmc;
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/* PKGC MSRs are common across Intel Core SoCs */
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static const struct pmc_bit_map msr_map[] = {
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{"Package C2", MSR_PKG_C2_RESIDENCY},
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{"Package C3", MSR_PKG_C3_RESIDENCY},
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{"Package C6", MSR_PKG_C6_RESIDENCY},
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{"Package C7", MSR_PKG_C7_RESIDENCY},
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{"Package C8", MSR_PKG_C8_RESIDENCY},
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{"Package C9", MSR_PKG_C9_RESIDENCY},
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{"Package C10", MSR_PKG_C10_RESIDENCY},
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{}
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};
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static const struct pmc_bit_map spt_pll_map[] = {
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{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
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{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
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{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
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{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
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{}
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};
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static const struct pmc_bit_map spt_mphy_map[] = {
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{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
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{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
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{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
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{"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
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{"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
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{"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
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{"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
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{"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
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{"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
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{"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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{"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
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{"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
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{"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
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{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
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{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
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{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
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{}
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};
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static const struct pmc_bit_map spt_pfear_map[] = {
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{"PMC", SPT_PMC_BIT_PMC},
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{"OPI-DMI", SPT_PMC_BIT_OPI},
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{"SPI / eSPI", SPT_PMC_BIT_SPI},
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{"XHCI", SPT_PMC_BIT_XHCI},
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{"SPA", SPT_PMC_BIT_SPA},
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{"SPB", SPT_PMC_BIT_SPB},
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{"SPC", SPT_PMC_BIT_SPC},
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{"GBE", SPT_PMC_BIT_GBE},
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{"SATA", SPT_PMC_BIT_SATA},
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{"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
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{"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
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{"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
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{"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
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{"RSVD", SPT_PMC_BIT_RSVD_0B},
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{"LPSS", SPT_PMC_BIT_LPSS},
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{"LPC", SPT_PMC_BIT_LPC},
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{"SMB", SPT_PMC_BIT_SMB},
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{"ISH", SPT_PMC_BIT_ISH},
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{"P2SB", SPT_PMC_BIT_P2SB},
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{"DFX", SPT_PMC_BIT_DFX},
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{"SCC", SPT_PMC_BIT_SCC},
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{"RSVD", SPT_PMC_BIT_RSVD_0C},
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{"FUSE", SPT_PMC_BIT_FUSE},
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{"CAMERA", SPT_PMC_BIT_CAMREA},
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{"RSVD", SPT_PMC_BIT_RSVD_0D},
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{"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
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{"EXI", SPT_PMC_BIT_EXI},
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{"CSE", SPT_PMC_BIT_CSE},
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{"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
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{"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
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{"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
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{"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
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{"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
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{"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
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{"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
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{"RSVD", SPT_PMC_BIT_RSVD_1A},
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{"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
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{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
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{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
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{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
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{}
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};
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static const struct pmc_bit_map *ext_spt_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of spt_reg_map for
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* a list of core SoCs using this.
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*/
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spt_pfear_map,
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NULL
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};
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static const struct pmc_bit_map spt_ltr_show_map[] = {
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{"SOUTHPORT_A", SPT_PMC_LTR_SPA},
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{"SOUTHPORT_B", SPT_PMC_LTR_SPB},
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{"SATA", SPT_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
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{"XHCI", SPT_PMC_LTR_XHCI},
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{"Reserved", SPT_PMC_LTR_RESERVED},
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{"ME", SPT_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"EVA", SPT_PMC_LTR_EVA},
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{"SOUTHPORT_C", SPT_PMC_LTR_SPC},
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{"HD_AUDIO", SPT_PMC_LTR_AZ},
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{"LPSS", SPT_PMC_LTR_LPSS},
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{"SOUTHPORT_D", SPT_PMC_LTR_SPD},
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{"SOUTHPORT_E", SPT_PMC_LTR_SPE},
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{"CAMERA", SPT_PMC_LTR_CAM},
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{"ESPI", SPT_PMC_LTR_ESPI},
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{"SCC", SPT_PMC_LTR_SCC},
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{"ISH", SPT_PMC_LTR_ISH},
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/* Below two cannot be used for LTR_IGNORE */
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{"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
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{"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
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{}
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};
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static const struct pmc_reg_map spt_reg_map = {
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.pfear_sts = ext_spt_pfear_map,
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.mphy_sts = spt_mphy_map,
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.pll_sts = spt_pll_map,
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.ltr_show_sts = spt_ltr_show_map,
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.msr_sts = msr_map,
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.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
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.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = SPT_PMC_MMIO_REG_LEN,
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.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
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.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
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.pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
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};
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/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
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static const struct pmc_bit_map cnp_pfear_map[] = {
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{"PMC", BIT(0)},
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{"OPI-DMI", BIT(1)},
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{"SPI/eSPI", BIT(2)},
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{"XHCI", BIT(3)},
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{"SPA", BIT(4)},
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{"SPB", BIT(5)},
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{"SPC", BIT(6)},
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{"GBE", BIT(7)},
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{"SATA", BIT(0)},
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{"HDA_PGD0", BIT(1)},
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{"HDA_PGD1", BIT(2)},
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{"HDA_PGD2", BIT(3)},
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{"HDA_PGD3", BIT(4)},
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{"SPD", BIT(5)},
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{"LPSS", BIT(6)},
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{"LPC", BIT(7)},
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{"SMB", BIT(0)},
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{"ISH", BIT(1)},
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{"P2SB", BIT(2)},
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{"NPK_VNN", BIT(3)},
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{"SDX", BIT(4)},
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{"SPE", BIT(5)},
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{"Fuse", BIT(6)},
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{"SBR8", BIT(7)},
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{"CSME_FSC", BIT(0)},
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{"USB3_OTG", BIT(1)},
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{"EXI", BIT(2)},
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{"CSE", BIT(3)},
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{"CSME_KVM", BIT(4)},
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{"CSME_PMT", BIT(5)},
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{"CSME_CLINK", BIT(6)},
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{"CSME_PTIO", BIT(7)},
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{"CSME_USBR", BIT(0)},
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{"CSME_SUSRAM", BIT(1)},
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{"CSME_SMT1", BIT(2)},
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{"CSME_SMT4", BIT(3)},
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{"CSME_SMS2", BIT(4)},
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{"CSME_SMS1", BIT(5)},
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{"CSME_RTC", BIT(6)},
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{"CSME_PSF", BIT(7)},
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{"SBR0", BIT(0)},
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{"SBR1", BIT(1)},
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{"SBR2", BIT(2)},
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{"SBR3", BIT(3)},
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{"SBR4", BIT(4)},
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{"SBR5", BIT(5)},
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{"CSME_PECI", BIT(6)},
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{"PSF1", BIT(7)},
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{"PSF2", BIT(0)},
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{"PSF3", BIT(1)},
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{"PSF4", BIT(2)},
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{"CNVI", BIT(3)},
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{"UFS0", BIT(4)},
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{"EMMC", BIT(5)},
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{"SPF", BIT(6)},
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{"SBR6", BIT(7)},
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{"SBR7", BIT(0)},
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{"NPK_AON", BIT(1)},
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{"HDA_PGD4", BIT(2)},
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{"HDA_PGD5", BIT(3)},
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{"HDA_PGD6", BIT(4)},
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{"PSF6", BIT(5)},
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{"PSF7", BIT(6)},
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{"PSF8", BIT(7)},
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{}
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};
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static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of cnp_reg_map for
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* a list of core SoCs using this.
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*/
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cnp_pfear_map,
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NULL
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};
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static const struct pmc_bit_map icl_pfear_map[] = {
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{"RES_65", BIT(0)},
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{"RES_66", BIT(1)},
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{"RES_67", BIT(2)},
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{"TAM", BIT(3)},
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{"GBETSN", BIT(4)},
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{"TBTLSX", BIT(5)},
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{"RES_71", BIT(6)},
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{"RES_72", BIT(7)},
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{}
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};
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static const struct pmc_bit_map *ext_icl_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of icl_reg_map for
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* a list of core SoCs using this.
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*/
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cnp_pfear_map,
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icl_pfear_map,
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NULL
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};
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static const struct pmc_bit_map tgl_pfear_map[] = {
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{"PSF9", BIT(0)},
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{"RES_66", BIT(1)},
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{"RES_67", BIT(2)},
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{"RES_68", BIT(3)},
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{"RES_69", BIT(4)},
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{"RES_70", BIT(5)},
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{"TBTLSX", BIT(6)},
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{}
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};
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static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of tgl_reg_map for
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* a list of core SoCs using this.
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*/
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cnp_pfear_map,
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tgl_pfear_map,
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NULL
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};
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static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
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{"AUDIO_D3", BIT(0)},
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{"OTG_D3", BIT(1)},
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{"XHCI_D3", BIT(2)},
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{"LPIO_D3", BIT(3)},
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{"SDX_D3", BIT(4)},
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{"SATA_D3", BIT(5)},
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{"UFS0_D3", BIT(6)},
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{"UFS1_D3", BIT(7)},
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{"EMMC_D3", BIT(8)},
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{}
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};
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static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
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{"SDIO_PLL_OFF", BIT(0)},
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{"USB2_PLL_OFF", BIT(1)},
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{"AUDIO_PLL_OFF", BIT(2)},
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{"OC_PLL_OFF", BIT(3)},
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{"MAIN_PLL_OFF", BIT(4)},
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{"XOSC_OFF", BIT(5)},
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{"LPC_CLKS_GATED", BIT(6)},
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{"PCIE_CLKREQS_IDLE", BIT(7)},
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{"AUDIO_ROSC_OFF", BIT(8)},
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{"HPET_XOSC_CLK_REQ", BIT(9)},
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{"PMC_ROSC_SLOW_CLK", BIT(10)},
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{"AON2_ROSC_GATED", BIT(11)},
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{"CLKACKS_DEASSERTED", BIT(12)},
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{}
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};
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static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
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{"MPHY_CORE_GATED", BIT(0)},
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{"CSME_GATED", BIT(1)},
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{"USB2_SUS_GATED", BIT(2)},
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{"DYN_FLEX_IO_IDLE", BIT(3)},
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{"GBE_NO_LINK", BIT(4)},
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{"THERM_SEN_DISABLED", BIT(5)},
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{"PCIE_LOW_POWER", BIT(6)},
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{"ISH_VNNAON_REQ_ACT", BIT(7)},
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{"ISH_VNN_REQ_ACT", BIT(8)},
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{"CNV_VNNAON_REQ_ACT", BIT(9)},
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{"CNV_VNN_REQ_ACT", BIT(10)},
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{"NPK_VNNON_REQ_ACT", BIT(11)},
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{"PMSYNC_STATE_IDLE", BIT(12)},
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{"ALST_GT_THRES", BIT(13)},
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{"PMC_ARC_PG_READY", BIT(14)},
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{}
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};
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static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
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cnp_slps0_dbg0_map,
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cnp_slps0_dbg1_map,
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cnp_slps0_dbg2_map,
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NULL
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};
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static const struct pmc_bit_map cnp_ltr_show_map[] = {
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{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
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{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
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{"SATA", CNP_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
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{"XHCI", CNP_PMC_LTR_XHCI},
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{"Reserved", CNP_PMC_LTR_RESERVED},
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{"ME", CNP_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"EVA", CNP_PMC_LTR_EVA},
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{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
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{"HD_AUDIO", CNP_PMC_LTR_AZ},
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{"CNV", CNP_PMC_LTR_CNV},
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{"LPSS", CNP_PMC_LTR_LPSS},
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{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
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{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
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{"CAMERA", CNP_PMC_LTR_CAM},
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{"ESPI", CNP_PMC_LTR_ESPI},
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{"SCC", CNP_PMC_LTR_SCC},
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{"ISH", CNP_PMC_LTR_ISH},
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{"UFSX2", CNP_PMC_LTR_UFSX2},
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{"EMMC", CNP_PMC_LTR_EMMC},
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/*
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* Check intel_pmc_core_ids[] users of cnp_reg_map for
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* a list of core SoCs using this.
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*/
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{"WIGIG", ICL_PMC_LTR_WIGIG},
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/* Below two cannot be used for LTR_IGNORE */
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{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
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{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
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{}
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};
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static const struct pmc_reg_map cnp_reg_map = {
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.pfear_sts = ext_cnp_pfear_map,
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.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
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.slps0_dbg_maps = cnp_slps0_dbg_maps,
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.ltr_show_sts = cnp_ltr_show_map,
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.msr_sts = msr_map,
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.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = CNP_PMC_MMIO_REG_LEN,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
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};
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static const struct pmc_reg_map icl_reg_map = {
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.pfear_sts = ext_icl_pfear_map,
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.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
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.slps0_dbg_maps = cnp_slps0_dbg_maps,
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.ltr_show_sts = cnp_ltr_show_map,
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.msr_sts = msr_map,
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.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = CNP_PMC_MMIO_REG_LEN,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
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};
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static const struct pmc_bit_map tgl_clocksource_status_map[] = {
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{"USB2PLL_OFF_STS", BIT(18)},
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{"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
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{"PCIe_Gen3PLL_OFF_STS", BIT(20)},
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{"OPIOPLL_OFF_STS", BIT(21)},
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{"OCPLL_OFF_STS", BIT(22)},
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{"MainPLL_OFF_STS", BIT(23)},
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{"MIPIPLL_OFF_STS", BIT(24)},
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{"Fast_XTAL_Osc_OFF_STS", BIT(25)},
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{"AC_Ring_Osc_OFF_STS", BIT(26)},
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{"MC_Ring_Osc_OFF_STS", BIT(27)},
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{"SATAPLL_OFF_STS", BIT(29)},
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{"XTAL_USB2PLL_OFF_STS", BIT(31)},
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{}
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};
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static const struct pmc_bit_map tgl_power_gating_status_map[] = {
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{"CSME_PG_STS", BIT(0)},
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{"SATA_PG_STS", BIT(1)},
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{"xHCI_PG_STS", BIT(2)},
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{"UFSX2_PG_STS", BIT(3)},
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{"OTG_PG_STS", BIT(5)},
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{"SPA_PG_STS", BIT(6)},
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{"SPB_PG_STS", BIT(7)},
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{"SPC_PG_STS", BIT(8)},
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{"SPD_PG_STS", BIT(9)},
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{"SPE_PG_STS", BIT(10)},
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{"SPF_PG_STS", BIT(11)},
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{"LSX_PG_STS", BIT(13)},
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{"P2SB_PG_STS", BIT(14)},
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{"PSF_PG_STS", BIT(15)},
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{"SBR_PG_STS", BIT(16)},
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{"OPIDMI_PG_STS", BIT(17)},
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{"THC0_PG_STS", BIT(18)},
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{"THC1_PG_STS", BIT(19)},
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{"GBETSN_PG_STS", BIT(20)},
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{"GBE_PG_STS", BIT(21)},
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{"LPSS_PG_STS", BIT(22)},
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{"MMP_UFSX2_PG_STS", BIT(23)},
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{"MMP_UFSX2B_PG_STS", BIT(24)},
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{"FIA_PG_STS", BIT(25)},
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{}
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};
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static const struct pmc_bit_map tgl_d3_status_map[] = {
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{"ADSP_D3_STS", BIT(0)},
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{"SATA_D3_STS", BIT(1)},
|
{"xHCI0_D3_STS", BIT(2)},
|
{"xDCI1_D3_STS", BIT(5)},
|
{"SDX_D3_STS", BIT(6)},
|
{"EMMC_D3_STS", BIT(7)},
|
{"IS_D3_STS", BIT(8)},
|
{"THC0_D3_STS", BIT(9)},
|
{"THC1_D3_STS", BIT(10)},
|
{"GBE_D3_STS", BIT(11)},
|
{"GBE_TSN_D3_STS", BIT(12)},
|
{}
|
};
|
|
static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
|
{"GPIO_COM0_VNN_REQ_STS", BIT(1)},
|
{"GPIO_COM1_VNN_REQ_STS", BIT(2)},
|
{"GPIO_COM2_VNN_REQ_STS", BIT(3)},
|
{"GPIO_COM3_VNN_REQ_STS", BIT(4)},
|
{"GPIO_COM4_VNN_REQ_STS", BIT(5)},
|
{"GPIO_COM5_VNN_REQ_STS", BIT(6)},
|
{"Audio_VNN_REQ_STS", BIT(7)},
|
{"ISH_VNN_REQ_STS", BIT(8)},
|
{"CNVI_VNN_REQ_STS", BIT(9)},
|
{"eSPI_VNN_REQ_STS", BIT(10)},
|
{"Display_VNN_REQ_STS", BIT(11)},
|
{"DTS_VNN_REQ_STS", BIT(12)},
|
{"SMBUS_VNN_REQ_STS", BIT(14)},
|
{"CSME_VNN_REQ_STS", BIT(15)},
|
{"SMLINK0_VNN_REQ_STS", BIT(16)},
|
{"SMLINK1_VNN_REQ_STS", BIT(17)},
|
{"CLINK_VNN_REQ_STS", BIT(20)},
|
{"DCI_VNN_REQ_STS", BIT(21)},
|
{"ITH_VNN_REQ_STS", BIT(22)},
|
{"CSME_VNN_REQ_STS", BIT(24)},
|
{"GBE_VNN_REQ_STS", BIT(25)},
|
{}
|
};
|
|
static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
|
{"CPU_C10_REQ_STS_0", BIT(0)},
|
{"PCIe_LPM_En_REQ_STS_3", BIT(3)},
|
{"ITH_REQ_STS_5", BIT(5)},
|
{"CNVI_REQ_STS_6", BIT(6)},
|
{"ISH_REQ_STS_7", BIT(7)},
|
{"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)},
|
{"PCIe_Clk_REQ_STS_12", BIT(12)},
|
{"MPHY_Core_DL_REQ_STS_16", BIT(16)},
|
{"Break-even_En_REQ_STS_17", BIT(17)},
|
{"Auto-demo_En_REQ_STS_18", BIT(18)},
|
{"MPHY_SUS_REQ_STS_22", BIT(22)},
|
{"xDCI_attached_REQ_STS_24", BIT(24)},
|
{}
|
};
|
|
static const struct pmc_bit_map tgl_signal_status_map[] = {
|
{"LSX_Wake0_En_STS", BIT(0)},
|
{"LSX_Wake0_Pol_STS", BIT(1)},
|
{"LSX_Wake1_En_STS", BIT(2)},
|
{"LSX_Wake1_Pol_STS", BIT(3)},
|
{"LSX_Wake2_En_STS", BIT(4)},
|
{"LSX_Wake2_Pol_STS", BIT(5)},
|
{"LSX_Wake3_En_STS", BIT(6)},
|
{"LSX_Wake3_Pol_STS", BIT(7)},
|
{"LSX_Wake4_En_STS", BIT(8)},
|
{"LSX_Wake4_Pol_STS", BIT(9)},
|
{"LSX_Wake5_En_STS", BIT(10)},
|
{"LSX_Wake5_Pol_STS", BIT(11)},
|
{"LSX_Wake6_En_STS", BIT(12)},
|
{"LSX_Wake6_Pol_STS", BIT(13)},
|
{"LSX_Wake7_En_STS", BIT(14)},
|
{"LSX_Wake7_Pol_STS", BIT(15)},
|
{"Intel_Se_IO_Wake0_En_STS", BIT(16)},
|
{"Intel_Se_IO_Wake0_Pol_STS", BIT(17)},
|
{"Intel_Se_IO_Wake1_En_STS", BIT(18)},
|
{"Intel_Se_IO_Wake1_Pol_STS", BIT(19)},
|
{"Int_Timer_SS_Wake0_En_STS", BIT(20)},
|
{"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
|
{"Int_Timer_SS_Wake1_En_STS", BIT(22)},
|
{"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
|
{"Int_Timer_SS_Wake2_En_STS", BIT(24)},
|
{"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
|
{"Int_Timer_SS_Wake3_En_STS", BIT(26)},
|
{"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
|
{"Int_Timer_SS_Wake4_En_STS", BIT(28)},
|
{"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
|
{"Int_Timer_SS_Wake5_En_STS", BIT(30)},
|
{"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},
|
{}
|
};
|
|
static const struct pmc_bit_map *tgl_lpm_maps[] = {
|
tgl_clocksource_status_map,
|
tgl_power_gating_status_map,
|
tgl_d3_status_map,
|
tgl_vnn_req_status_map,
|
tgl_vnn_misc_status_map,
|
tgl_signal_status_map,
|
NULL
|
};
|
|
static const struct pmc_reg_map tgl_reg_map = {
|
.pfear_sts = ext_tgl_pfear_map,
|
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
|
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
|
.ltr_show_sts = cnp_ltr_show_map,
|
.msr_sts = msr_map,
|
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
|
.regmap_length = CNP_PMC_MMIO_REG_LEN,
|
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
|
.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
|
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
|
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
|
.ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
|
.lpm_modes = tgl_lpm_modes,
|
.lpm_en_offset = TGL_LPM_EN_OFFSET,
|
.lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
|
.lpm_sts = tgl_lpm_maps,
|
.lpm_status_offset = TGL_LPM_STATUS_OFFSET,
|
.lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
|
};
|
|
static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
|
{
|
return readl(pmcdev->regbase + reg_offset);
|
}
|
|
static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
|
u32 val)
|
{
|
writel(val, pmcdev->regbase + reg_offset);
|
}
|
|
static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
|
{
|
return (u64)value * pmcdev->map->slp_s0_res_counter_step;
|
}
|
|
static int pmc_core_dev_state_get(void *data, u64 *val)
|
{
|
struct pmc_dev *pmcdev = data;
|
const struct pmc_reg_map *map = pmcdev->map;
|
u32 value;
|
|
value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
|
*val = pmc_core_adjust_slp_s0_step(pmcdev, value);
|
|
return 0;
|
}
|
|
DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
|
|
static int pmc_core_check_read_lock_bit(void)
|
{
|
struct pmc_dev *pmcdev = &pmc;
|
u32 value;
|
|
value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
|
return value & BIT(pmcdev->map->pm_read_disable_bit);
|
}
|
|
static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
|
struct seq_file *s)
|
{
|
const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
|
const struct pmc_bit_map *map;
|
int offset = pmcdev->map->slps0_dbg_offset;
|
u32 data;
|
|
while (*maps) {
|
map = *maps;
|
data = pmc_core_reg_read(pmcdev, offset);
|
offset += 4;
|
while (map->name) {
|
if (dev)
|
dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
|
map->name,
|
data & map->bit_mask ? "Yes" : "No");
|
if (s)
|
seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
|
map->name,
|
data & map->bit_mask ? "Yes" : "No");
|
++map;
|
}
|
++maps;
|
}
|
}
|
|
static int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps)
|
{
|
int idx;
|
|
for (idx = 0; maps[idx]; idx++)
|
;/* Nothing */
|
|
return idx;
|
}
|
|
static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
|
struct seq_file *s, u32 offset,
|
const char *str,
|
const struct pmc_bit_map **maps)
|
{
|
int index, idx, len = 32, bit_mask, arr_size;
|
u32 *lpm_regs;
|
|
arr_size = pmc_core_lpm_get_arr_size(maps);
|
lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL);
|
if (!lpm_regs)
|
return;
|
|
for (index = 0; index < arr_size; index++) {
|
lpm_regs[index] = pmc_core_reg_read(pmcdev, offset);
|
offset += 4;
|
}
|
|
for (idx = 0; idx < arr_size; idx++) {
|
if (dev)
|
dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
|
lpm_regs[idx]);
|
if (s)
|
seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
|
lpm_regs[idx]);
|
for (index = 0; maps[idx][index].name && index < len; index++) {
|
bit_mask = maps[idx][index].bit_mask;
|
if (dev)
|
dev_info(dev, "%-30s %-30d\n",
|
maps[idx][index].name,
|
lpm_regs[idx] & bit_mask ? 1 : 0);
|
if (s)
|
seq_printf(s, "%-30s %-30d\n",
|
maps[idx][index].name,
|
lpm_regs[idx] & bit_mask ? 1 : 0);
|
}
|
}
|
|
kfree(lpm_regs);
|
}
|
|
static bool slps0_dbg_latch;
|
|
static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
|
{
|
return readb(pmcdev->regbase + offset);
|
}
|
|
static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
|
u8 pf_reg, const struct pmc_bit_map **pf_map)
|
{
|
seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
|
ip, pf_map[idx][index].name,
|
pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
|
}
|
|
static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const struct pmc_bit_map **maps = pmcdev->map->pfear_sts;
|
u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
|
int index, iter, idx, ip = 0;
|
|
iter = pmcdev->map->ppfear0_offset;
|
|
for (index = 0; index < pmcdev->map->ppfear_buckets &&
|
index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
|
pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
|
|
for (idx = 0; maps[idx]; idx++) {
|
for (index = 0; maps[idx][index].name &&
|
index < pmcdev->map->ppfear_buckets * 8; ip++, index++)
|
pmc_core_display_map(s, index, idx, ip,
|
pf_regs[index / 8], maps);
|
}
|
|
return 0;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
|
|
/* This function should return link status, 0 means ready */
|
static int pmc_core_mtpmc_link_status(void)
|
{
|
struct pmc_dev *pmcdev = &pmc;
|
u32 value;
|
|
value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
|
return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
|
}
|
|
static int pmc_core_send_msg(u32 *addr_xram)
|
{
|
struct pmc_dev *pmcdev = &pmc;
|
u32 dest;
|
int timeout;
|
|
for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
|
if (pmc_core_mtpmc_link_status() == 0)
|
break;
|
msleep(5);
|
}
|
|
if (timeout <= 0 && pmc_core_mtpmc_link_status())
|
return -EBUSY;
|
|
dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
|
pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
|
return 0;
|
}
|
|
static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
|
u32 mphy_core_reg_low, mphy_core_reg_high;
|
u32 val_low, val_high;
|
int index, err = 0;
|
|
if (pmcdev->pmc_xram_read_bit) {
|
seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
|
return 0;
|
}
|
|
mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
|
mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
|
|
mutex_lock(&pmcdev->lock);
|
|
if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
|
err = -EBUSY;
|
goto out_unlock;
|
}
|
|
msleep(10);
|
val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
|
|
if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
|
err = -EBUSY;
|
goto out_unlock;
|
}
|
|
msleep(10);
|
val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
|
|
for (index = 0; index < 8 && map[index].name; index++) {
|
seq_printf(s, "%-32s\tState: %s\n",
|
map[index].name,
|
map[index].bit_mask & val_low ? "Not power gated" :
|
"Power gated");
|
}
|
|
for (index = 8; map[index].name; index++) {
|
seq_printf(s, "%-32s\tState: %s\n",
|
map[index].name,
|
map[index].bit_mask & val_high ? "Not power gated" :
|
"Power gated");
|
}
|
|
out_unlock:
|
mutex_unlock(&pmcdev->lock);
|
return err;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
|
|
static int pmc_core_pll_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const struct pmc_bit_map *map = pmcdev->map->pll_sts;
|
u32 mphy_common_reg, val;
|
int index, err = 0;
|
|
if (pmcdev->pmc_xram_read_bit) {
|
seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
|
return 0;
|
}
|
|
mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
|
mutex_lock(&pmcdev->lock);
|
|
if (pmc_core_send_msg(&mphy_common_reg) != 0) {
|
err = -EBUSY;
|
goto out_unlock;
|
}
|
|
/* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
|
msleep(10);
|
val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
|
|
for (index = 0; map[index].name ; index++) {
|
seq_printf(s, "%-32s\tState: %s\n",
|
map[index].name,
|
map[index].bit_mask & val ? "Active" : "Idle");
|
}
|
|
out_unlock:
|
mutex_unlock(&pmcdev->lock);
|
return err;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
|
|
static int pmc_core_send_ltr_ignore(u32 value)
|
{
|
struct pmc_dev *pmcdev = &pmc;
|
const struct pmc_reg_map *map = pmcdev->map;
|
u32 reg;
|
int err = 0;
|
|
mutex_lock(&pmcdev->lock);
|
|
if (value > map->ltr_ignore_max) {
|
err = -EINVAL;
|
goto out_unlock;
|
}
|
|
reg = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
|
reg |= BIT(value);
|
pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, reg);
|
|
out_unlock:
|
mutex_unlock(&pmcdev->lock);
|
|
return err;
|
}
|
|
static ssize_t pmc_core_ltr_ignore_write(struct file *file,
|
const char __user *userbuf,
|
size_t count, loff_t *ppos)
|
{
|
u32 buf_size, value;
|
int err;
|
|
buf_size = min_t(u32, count, 64);
|
|
err = kstrtou32_from_user(userbuf, buf_size, 10, &value);
|
if (err)
|
return err;
|
|
err = pmc_core_send_ltr_ignore(value);
|
|
return err == 0 ? count : err;
|
}
|
|
static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
|
{
|
return 0;
|
}
|
|
static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
|
{
|
return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
|
}
|
|
static const struct file_operations pmc_core_ltr_ignore_ops = {
|
.open = pmc_core_ltr_ignore_open,
|
.read = seq_read,
|
.write = pmc_core_ltr_ignore_write,
|
.llseek = seq_lseek,
|
.release = single_release,
|
};
|
|
static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
|
{
|
const struct pmc_reg_map *map = pmcdev->map;
|
u32 fd;
|
|
mutex_lock(&pmcdev->lock);
|
|
if (!reset && !slps0_dbg_latch)
|
goto out_unlock;
|
|
fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
|
if (reset)
|
fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
|
else
|
fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
|
pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
|
|
slps0_dbg_latch = 0;
|
|
out_unlock:
|
mutex_unlock(&pmcdev->lock);
|
}
|
|
static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
|
pmc_core_slps0_dbg_latch(pmcdev, false);
|
pmc_core_slps0_display(pmcdev, NULL, s);
|
pmc_core_slps0_dbg_latch(pmcdev, true);
|
|
return 0;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
|
|
static u32 convert_ltr_scale(u32 val)
|
{
|
/*
|
* As per PCIE specification supporting document
|
* ECN_LatencyTolnReporting_14Aug08.pdf the Latency
|
* Tolerance Reporting data payload is encoded in a
|
* 3 bit scale and 10 bit value fields. Values are
|
* multiplied by the indicated scale to yield an absolute time
|
* value, expressible in a range from 1 nanosecond to
|
* 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
|
*
|
* scale encoding is as follows:
|
*
|
* ----------------------------------------------
|
* |scale factor | Multiplier (ns) |
|
* ----------------------------------------------
|
* | 0 | 1 |
|
* | 1 | 32 |
|
* | 2 | 1024 |
|
* | 3 | 32768 |
|
* | 4 | 1048576 |
|
* | 5 | 33554432 |
|
* | 6 | Invalid |
|
* | 7 | Invalid |
|
* ----------------------------------------------
|
*/
|
if (val > 5) {
|
pr_warn("Invalid LTR scale factor.\n");
|
return 0;
|
}
|
|
return 1U << (5 * val);
|
}
|
|
static int pmc_core_ltr_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
|
u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
|
u32 ltr_raw_data, scale, val;
|
u16 snoop_ltr, nonsnoop_ltr;
|
int index;
|
|
for (index = 0; map[index].name ; index++) {
|
decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
|
ltr_raw_data = pmc_core_reg_read(pmcdev,
|
map[index].bit_mask);
|
snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
|
nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
|
|
if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
|
scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
|
val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
|
decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
|
}
|
|
if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
|
scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
|
val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
|
decoded_snoop_ltr = val * convert_ltr_scale(scale);
|
}
|
|
seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
|
map[index].name, ltr_raw_data,
|
decoded_non_snoop_ltr,
|
decoded_snoop_ltr);
|
}
|
return 0;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
|
|
static int pmc_core_substate_res_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const char **lpm_modes = pmcdev->map->lpm_modes;
|
u32 offset = pmcdev->map->lpm_residency_offset;
|
u32 lpm_en;
|
int index;
|
|
lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
|
seq_printf(s, "status substate residency\n");
|
for (index = 0; lpm_modes[index]; index++) {
|
seq_printf(s, "%7s %7s %-15u\n",
|
BIT(index) & lpm_en ? "Enabled" : " ",
|
lpm_modes[index], pmc_core_reg_read(pmcdev, offset));
|
offset += 4;
|
}
|
|
return 0;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res);
|
|
static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
|
u32 offset = pmcdev->map->lpm_status_offset;
|
|
pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps);
|
|
return 0;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs);
|
|
static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
|
u32 offset = pmcdev->map->lpm_live_status_offset;
|
|
pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps);
|
|
return 0;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs);
|
|
static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
|
{
|
struct pmc_dev *pmcdev = s->private;
|
const struct pmc_bit_map *map = pmcdev->map->msr_sts;
|
u64 pcstate_count;
|
int index;
|
|
for (index = 0; map[index].name ; index++) {
|
if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
|
continue;
|
|
pcstate_count *= 1000;
|
do_div(pcstate_count, tsc_khz);
|
seq_printf(s, "%-8s : %llu\n", map[index].name,
|
pcstate_count);
|
}
|
|
return 0;
|
}
|
DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
|
|
static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
|
{
|
debugfs_remove_recursive(pmcdev->dbgfs_dir);
|
}
|
|
static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
|
{
|
struct dentry *dir;
|
|
dir = debugfs_create_dir("pmc_core", NULL);
|
pmcdev->dbgfs_dir = dir;
|
|
debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
|
&pmc_core_dev_state);
|
|
if (pmcdev->map->pfear_sts)
|
debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
|
pmcdev, &pmc_core_ppfear_fops);
|
|
debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
|
&pmc_core_ltr_ignore_ops);
|
|
debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
|
|
debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
|
&pmc_core_pkgc_fops);
|
|
if (pmcdev->map->pll_sts)
|
debugfs_create_file("pll_status", 0444, dir, pmcdev,
|
&pmc_core_pll_fops);
|
|
if (pmcdev->map->mphy_sts)
|
debugfs_create_file("mphy_core_lanes_power_gating_status",
|
0444, dir, pmcdev,
|
&pmc_core_mphy_pg_fops);
|
|
if (pmcdev->map->slps0_dbg_maps) {
|
debugfs_create_file("slp_s0_debug_status", 0444,
|
dir, pmcdev,
|
&pmc_core_slps0_dbg_fops);
|
|
debugfs_create_bool("slp_s0_dbg_latch", 0644,
|
dir, &slps0_dbg_latch);
|
}
|
|
if (pmcdev->map->lpm_en_offset) {
|
debugfs_create_file("substate_residencies", 0444,
|
pmcdev->dbgfs_dir, pmcdev,
|
&pmc_core_substate_res_fops);
|
}
|
|
if (pmcdev->map->lpm_status_offset) {
|
debugfs_create_file("substate_status_registers", 0444,
|
pmcdev->dbgfs_dir, pmcdev,
|
&pmc_core_substate_sts_regs_fops);
|
debugfs_create_file("substate_live_status_registers", 0444,
|
pmcdev->dbgfs_dir, pmcdev,
|
&pmc_core_substate_l_sts_regs_fops);
|
}
|
}
|
|
static const struct x86_cpu_id intel_pmc_core_ids[] = {
|
X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &spt_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &spt_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &spt_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &spt_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &cnp_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &icl_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &cnp_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &cnp_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
|
X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map),
|
{}
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
|
|
static const struct pci_device_id pmc_pci_ids[] = {
|
{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
|
{ }
|
};
|
|
/*
|
* This quirk can be used on those platforms where
|
* the platform BIOS enforces 24Mhz crystal to shutdown
|
* before PMC can assert SLP_S0#.
|
*/
|
static bool xtal_ignore;
|
static int quirk_xtal_ignore(const struct dmi_system_id *id)
|
{
|
xtal_ignore = true;
|
return 0;
|
}
|
|
static void pmc_core_xtal_ignore(struct pmc_dev *pmcdev)
|
{
|
u32 value;
|
|
value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
|
/* 24MHz Crystal Shutdown Qualification Disable */
|
value |= SPT_PMC_VRIC1_XTALSDQDIS;
|
/* Low Voltage Mode Enable */
|
value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
|
pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
|
}
|
|
static const struct dmi_system_id pmc_core_dmi_table[] = {
|
{
|
.callback = quirk_xtal_ignore,
|
.ident = "HP Elite x2 1013 G3",
|
.matches = {
|
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
|
DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
|
},
|
},
|
{}
|
};
|
|
static void pmc_core_do_dmi_quirks(struct pmc_dev *pmcdev)
|
{
|
dmi_check_system(pmc_core_dmi_table);
|
|
if (xtal_ignore)
|
pmc_core_xtal_ignore(pmcdev);
|
}
|
|
static int pmc_core_probe(struct platform_device *pdev)
|
{
|
static bool device_initialized;
|
struct pmc_dev *pmcdev = &pmc;
|
const struct x86_cpu_id *cpu_id;
|
u64 slp_s0_addr;
|
|
if (device_initialized)
|
return -ENODEV;
|
|
cpu_id = x86_match_cpu(intel_pmc_core_ids);
|
if (!cpu_id)
|
return -ENODEV;
|
|
pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
|
|
/*
|
* Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
|
* Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
|
* in this case.
|
*/
|
if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
|
pmcdev->map = &cnp_reg_map;
|
|
if (lpit_read_residency_count_address(&slp_s0_addr)) {
|
pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
|
|
if (page_is_ram(PHYS_PFN(pmcdev->base_addr)))
|
return -ENODEV;
|
} else {
|
pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
|
}
|
|
pmcdev->regbase = ioremap(pmcdev->base_addr,
|
pmcdev->map->regmap_length);
|
if (!pmcdev->regbase)
|
return -ENOMEM;
|
|
mutex_init(&pmcdev->lock);
|
platform_set_drvdata(pdev, pmcdev);
|
pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
|
pmc_core_do_dmi_quirks(pmcdev);
|
|
/*
|
* On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when
|
* a cable is attached. Tell the PMC to ignore it.
|
*/
|
if (pmcdev->map == &tgl_reg_map) {
|
dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
|
pmc_core_send_ltr_ignore(3);
|
}
|
|
pmc_core_dbgfs_register(pmcdev);
|
|
device_initialized = true;
|
dev_info(&pdev->dev, " initialized\n");
|
|
return 0;
|
}
|
|
static int pmc_core_remove(struct platform_device *pdev)
|
{
|
struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
|
|
pmc_core_dbgfs_unregister(pmcdev);
|
platform_set_drvdata(pdev, NULL);
|
mutex_destroy(&pmcdev->lock);
|
iounmap(pmcdev->regbase);
|
return 0;
|
}
|
|
static bool warn_on_s0ix_failures;
|
module_param(warn_on_s0ix_failures, bool, 0644);
|
MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
|
|
static __maybe_unused int pmc_core_suspend(struct device *dev)
|
{
|
struct pmc_dev *pmcdev = dev_get_drvdata(dev);
|
|
pmcdev->check_counters = false;
|
|
/* No warnings on S0ix failures */
|
if (!warn_on_s0ix_failures)
|
return 0;
|
|
/* Check if the syspend will actually use S0ix */
|
if (pm_suspend_via_firmware())
|
return 0;
|
|
/* Save PC10 residency for checking later */
|
if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pmcdev->pc10_counter))
|
return -EIO;
|
|
/* Save S0ix residency for checking later */
|
if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter))
|
return -EIO;
|
|
pmcdev->check_counters = true;
|
return 0;
|
}
|
|
static inline bool pmc_core_is_pc10_failed(struct pmc_dev *pmcdev)
|
{
|
u64 pc10_counter;
|
|
if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pc10_counter))
|
return false;
|
|
if (pc10_counter == pmcdev->pc10_counter)
|
return true;
|
|
return false;
|
}
|
|
static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
|
{
|
u64 s0ix_counter;
|
|
if (pmc_core_dev_state_get(pmcdev, &s0ix_counter))
|
return false;
|
|
if (s0ix_counter == pmcdev->s0ix_counter)
|
return true;
|
|
return false;
|
}
|
|
static __maybe_unused int pmc_core_resume(struct device *dev)
|
{
|
struct pmc_dev *pmcdev = dev_get_drvdata(dev);
|
const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
|
int offset = pmcdev->map->lpm_status_offset;
|
|
if (!pmcdev->check_counters)
|
return 0;
|
|
if (!pmc_core_is_s0ix_failed(pmcdev))
|
return 0;
|
|
if (pmc_core_is_pc10_failed(pmcdev)) {
|
/* S0ix failed because of PC10 entry failure */
|
dev_info(dev, "CPU did not enter PC10!!! (PC10 cnt=0x%llx)\n",
|
pmcdev->pc10_counter);
|
return 0;
|
}
|
|
/* The real interesting case - S0ix failed - lets ask PMC why. */
|
dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
|
pmcdev->s0ix_counter);
|
if (pmcdev->map->slps0_dbg_maps)
|
pmc_core_slps0_display(pmcdev, dev, NULL);
|
if (pmcdev->map->lpm_sts)
|
pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps);
|
|
return 0;
|
}
|
|
static const struct dev_pm_ops pmc_core_pm_ops = {
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
|
};
|
|
static const struct acpi_device_id pmc_core_acpi_ids[] = {
|
{"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/
|
{ }
|
};
|
MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids);
|
|
static struct platform_driver pmc_core_driver = {
|
.driver = {
|
.name = "intel_pmc_core",
|
.acpi_match_table = ACPI_PTR(pmc_core_acpi_ids),
|
.pm = &pmc_core_pm_ops,
|
},
|
.probe = pmc_core_probe,
|
.remove = pmc_core_remove,
|
};
|
|
module_platform_driver(pmc_core_driver);
|
|
MODULE_LICENSE("GPL v2");
|
MODULE_DESCRIPTION("Intel PMC Core Driver");
|
