// SPDX-License-Identifier: GPL-2.0
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/*
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* Maxim max96755f pin control driver.
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*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/max96755f.h>
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#include "core.h"
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#include "pinconf.h"
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#include "pinmux.h"
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struct max96755f_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctl;
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struct regmap *regmap;
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};
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struct config_desc {
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u16 reg;
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u8 mask;
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u8 val;
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};
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struct max96755f_group_data {
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const struct config_desc *configs;
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int num_configs;
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};
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struct max96755f_function_data {
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u8 gpio_out_dis:1;
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u8 gpio_tx_en:1;
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u8 gpio_rx_en:1;
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u8 gpio_tx_id;
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u8 gpio_rx_id;
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};
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static int max96755f_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int function, unsigned int group)
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{
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struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
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struct function_desc *func;
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struct group_desc *grp;
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int i;
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func = pinmux_generic_get_function(pctldev, function);
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if (!func)
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return -EINVAL;
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grp = pinctrl_generic_get_group(pctldev, group);
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if (!grp)
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return -EINVAL;
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if (func->data) {
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struct max96755f_function_data *fdata = func->data;
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for (i = 0; i < grp->num_pins; i++) {
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regmap_update_bits(mpctl->regmap, GPIO_A_REG(grp->pins[i]),
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GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
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FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
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FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
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FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en));
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if (fdata->gpio_tx_en)
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regmap_update_bits(mpctl->regmap, GPIO_B_REG(grp->pins[i]),
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GPIO_TX_ID,
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FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
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if (fdata->gpio_rx_en)
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regmap_update_bits(mpctl->regmap, GPIO_C_REG(grp->pins[i]),
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GPIO_RX_ID,
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FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
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}
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}
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if (grp->data) {
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struct max96755f_group_data *gdata = grp->data;
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for (i = 0; i < gdata->num_configs; i++) {
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const struct config_desc *config = &gdata->configs[i];
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regmap_update_bits(mpctl->regmap, config->reg,
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config->mask, config->val);
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}
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}
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return 0;
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}
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static int max96755f_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *config)
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{
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struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned int gpio_a_reg, gpio_b_reg;
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u16 arg = 0;
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regmap_read(mpctl->regmap, GPIO_A_REG(pin), &gpio_a_reg);
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regmap_read(mpctl->regmap, GPIO_B_REG(pin), &gpio_b_reg);
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switch (param) {
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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if (FIELD_GET(OUT_TYPE, gpio_b_reg))
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
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return -EINVAL;
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
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return -EINVAL;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
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return -EINVAL;
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switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
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case 0:
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arg = 40000;
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break;
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case 1:
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arg = 10000;
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break;
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}
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
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return -EINVAL;
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switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
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case 0:
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arg = 40000;
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break;
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case 1:
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arg = 10000;
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break;
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}
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break;
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case PIN_CONFIG_OUTPUT:
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if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
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return -EINVAL;
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arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int max96755f_pinconf_set(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *configs,
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unsigned int num_configs)
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{
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struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param;
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u32 arg;
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u8 res_cfg;
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int i;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
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OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
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OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
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PULL_UPDN_SEL,
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FIELD_PREP(PULL_UPDN_SEL, 0));
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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switch (arg) {
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case 40000:
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res_cfg = 0;
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break;
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case 1000000:
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res_cfg = 1;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
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RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
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regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
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PULL_UPDN_SEL,
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FIELD_PREP(PULL_UPDN_SEL, 1));
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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switch (arg) {
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case 40000:
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res_cfg = 0;
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break;
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case 1000000:
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res_cfg = 1;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
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RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
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regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
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PULL_UPDN_SEL,
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FIELD_PREP(PULL_UPDN_SEL, 2));
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break;
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case PIN_CONFIG_OUTPUT:
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regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
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GPIO_OUT_DIS | GPIO_OUT,
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FIELD_PREP(GPIO_OUT_DIS, 0) |
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FIELD_PREP(GPIO_OUT, arg));
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break;
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default:
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return -ENOTSUPP;
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}
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}
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return 0;
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}
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static const struct pinconf_ops max96755f_pinconf_ops = {
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.pin_config_get = max96755f_pinconf_get,
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.pin_config_set = max96755f_pinconf_set,
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};
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static const struct pinmux_ops max96755f_pinmux_ops = {
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.get_functions_count = pinmux_generic_get_function_count,
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.get_function_name = pinmux_generic_get_function_name,
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.get_function_groups = pinmux_generic_get_function_groups,
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.set_mux = max96755f_pinmux_set_mux,
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};
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static const struct pinctrl_ops max96755f_pinctrl_ops = {
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.get_groups_count = pinctrl_generic_get_group_count,
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.get_group_name = pinctrl_generic_get_group_name,
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.get_group_pins = pinctrl_generic_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinconf_generic_dt_free_map,
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};
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static const struct pinctrl_pin_desc max96755f_pins_desc[] = {
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PINCTRL_PIN(0, "MFP0"),
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PINCTRL_PIN(1, "MFP1"),
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PINCTRL_PIN(2, "MFP2"),
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PINCTRL_PIN(3, "MFP3"),
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PINCTRL_PIN(4, "MFP4"),
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PINCTRL_PIN(5, "MFP5"),
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PINCTRL_PIN(6, "MFP6"),
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PINCTRL_PIN(7, "MFP7"),
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PINCTRL_PIN(8, "MFP8"),
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PINCTRL_PIN(9, "MFP9"),
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PINCTRL_PIN(10, "MFP10"),
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PINCTRL_PIN(11, "MFP11"),
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PINCTRL_PIN(12, "MFP12"),
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PINCTRL_PIN(13, "MFP13"),
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PINCTRL_PIN(14, "MFP14"),
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PINCTRL_PIN(15, "MFP15"),
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PINCTRL_PIN(16, "MFP16"),
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PINCTRL_PIN(17, "MFP17"),
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PINCTRL_PIN(18, "MFP18"),
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PINCTRL_PIN(19, "MFP19"),
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PINCTRL_PIN(20, "MFP20"),
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};
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static int MFP0_pins[] = {0};
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static int MFP1_pins[] = {1};
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static int MFP2_pins[] = {2};
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static int MFP3_pins[] = {3};
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static int MFP4_pins[] = {4};
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static int MFP5_pins[] = {5};
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static int MFP6_pins[] = {6};
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static int MFP7_pins[] = {7};
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static int MFP8_pins[] = {8};
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static int MFP9_pins[] = {9};
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static int MFP10_pins[] = {10};
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static int MFP11_pins[] = {11};
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static int MFP12_pins[] = {12};
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static int MFP13_pins[] = {13};
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static int MFP14_pins[] = {14};
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static int MFP15_pins[] = {15};
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static int MFP16_pins[] = {16};
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static int MFP17_pins[] = {17};
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static int MFP18_pins[] = {18};
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static int MFP19_pins[] = {19};
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static int MFP20_pins[] = {20};
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static int I2C_pins[] = {19, 20};
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static int UART_pins[] = {19, 20};
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#define GROUP_DESC(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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}
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#define GROUP_DESC_CONFIG(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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.data = (void *)(const struct max96755f_group_data []) { \
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{ \
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.configs = nm ## _configs, \
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.num_configs = ARRAY_SIZE(nm ## _configs), \
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} \
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}, \
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}
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static const struct config_desc MFP0_configs[] = {
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{ 0x0005, LOCK_EN, 0 },
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{ 0x0048, LOC_MS_EN, 0},
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};
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static const struct config_desc MFP1_configs[] = {
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{ 0x0005, ERRB_EN, 0 },
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};
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static const struct config_desc MFP4_configs[] = {
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{ 0x070, SPI_EN, 0 },
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};
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static const struct config_desc MFP5_configs[] = {
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{ 0x006, RCLKEN, 0 },
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};
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static const struct config_desc MFP7_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc MFP8_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc MFP9_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc MFP10_configs[] = {
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{ 0x0001, IIC_2_EN, 0 },
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{ 0x0003, UART_2_EN, 0 },
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{ 0x0140, AUD_RX_EN, 0},
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};
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static const struct config_desc MFP11_configs[] = {
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{ 0x0001, IIC_2_EN, 0 },
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{ 0x0003, UART_2_EN, 0 },
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{ 0x0140, AUD_RX_EN, 0},
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};
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static const struct config_desc MFP12_configs[] = {
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{ 0x0140, AUD_RX_EN, 0 },
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};
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static const struct config_desc MFP13_configs[] = {
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{ 0x0005, PU_LF0, 0 },
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};
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static const struct config_desc MFP14_configs[] = {
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{ 0x0005, PU_LF1, 0 },
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};
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static const struct config_desc MFP15_configs[] = {
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{ 0x0005, PU_LF2, 0 },
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};
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static const struct config_desc MFP16_configs[] = {
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{ 0x0005, PU_LF3, 0 },
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};
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static const struct config_desc MFP17_configs[] = {
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{ 0x0001, IIC_1_EN, 0 },
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{ 0x0003, UART_1_EN, 0 },
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};
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static const struct config_desc MFP18_configs[] = {
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{ 0x0001, IIC_1_EN, 0 },
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{ 0x0003, UART_1_EN, 0 },
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};
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static const struct group_desc max96755f_groups[] = {
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GROUP_DESC_CONFIG(MFP0),
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GROUP_DESC_CONFIG(MFP1),
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GROUP_DESC(MFP2),
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GROUP_DESC(MFP3),
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GROUP_DESC_CONFIG(MFP4),
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GROUP_DESC_CONFIG(MFP5),
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GROUP_DESC(MFP6),
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GROUP_DESC_CONFIG(MFP7),
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GROUP_DESC_CONFIG(MFP8),
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GROUP_DESC_CONFIG(MFP9),
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GROUP_DESC_CONFIG(MFP10),
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GROUP_DESC_CONFIG(MFP11),
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GROUP_DESC_CONFIG(MFP12),
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GROUP_DESC_CONFIG(MFP13),
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GROUP_DESC_CONFIG(MFP14),
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GROUP_DESC_CONFIG(MFP15),
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GROUP_DESC_CONFIG(MFP16),
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GROUP_DESC_CONFIG(MFP17),
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GROUP_DESC_CONFIG(MFP18),
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GROUP_DESC(MFP19),
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GROUP_DESC(MFP20),
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GROUP_DESC(I2C),
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GROUP_DESC(UART),
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};
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static const char *MFP_groups[] = {
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"MFP0", "MFP1", "MFP2", "MFP3", "MFP4", "MFP5",
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"MFP6", "MFP7", "MFP8", "MFP9", "MFP10",
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"MFP11", "MFP12", "MFP13", "MFP14", "MFP15",
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"MFP16", "MFP17", "MFP18", "MFP19", "MFP20",
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};
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static const char *I2C_groups[] = { "I2C" };
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static const char *UART_groups[] = { "UART" };
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#define FUNCTION_DESC(nm) \
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{ \
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.name = #nm, \
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.group_names = nm##_groups, \
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.num_group_names = ARRAY_SIZE(nm##_groups), \
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} \
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#define FUNCTION_DESC_GPIO() \
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{ \
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.name = "GPIO", \
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.group_names = MFP_groups, \
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.num_group_names = ARRAY_SIZE(MFP_groups), \
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.data = (void *)(const struct max96755f_function_data []) { \
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{ } \
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}, \
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} \
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#define FUNCTION_DESC_GPIO_RX(id) \
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{ \
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.name = "GPIO_RX_"#id, \
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.group_names = MFP_groups, \
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.num_group_names = ARRAY_SIZE(MFP_groups), \
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.data = (void *)(const struct max96755f_function_data []) { \
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{ .gpio_rx_en = 1, .gpio_rx_id = id } \
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}, \
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} \
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#define FUNCTION_DESC_GPIO_TX(id) \
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{ \
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.name = "GPIO_TX_"#id, \
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.group_names = MFP_groups, \
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.num_group_names = ARRAY_SIZE(MFP_groups), \
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.data = (void *)(const struct max96755f_function_data []) { \
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{ .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \
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}, \
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} \
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static const struct function_desc max96755f_functions[] = {
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FUNCTION_DESC_GPIO_TX(0),
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FUNCTION_DESC_GPIO_TX(1),
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FUNCTION_DESC_GPIO_TX(2),
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FUNCTION_DESC_GPIO_TX(3),
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FUNCTION_DESC_GPIO_TX(4),
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FUNCTION_DESC_GPIO_TX(5),
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FUNCTION_DESC_GPIO_TX(6),
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FUNCTION_DESC_GPIO_TX(7),
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FUNCTION_DESC_GPIO_TX(8),
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FUNCTION_DESC_GPIO_TX(9),
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FUNCTION_DESC_GPIO_TX(10),
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FUNCTION_DESC_GPIO_TX(11),
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FUNCTION_DESC_GPIO_TX(12),
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FUNCTION_DESC_GPIO_TX(13),
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FUNCTION_DESC_GPIO_TX(14),
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FUNCTION_DESC_GPIO_TX(15),
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FUNCTION_DESC_GPIO_TX(16),
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FUNCTION_DESC_GPIO_TX(17),
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FUNCTION_DESC_GPIO_TX(18),
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FUNCTION_DESC_GPIO_TX(19),
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FUNCTION_DESC_GPIO_TX(20),
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FUNCTION_DESC_GPIO_RX(0),
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FUNCTION_DESC_GPIO_RX(1),
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FUNCTION_DESC_GPIO_RX(2),
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FUNCTION_DESC_GPIO_RX(3),
|
FUNCTION_DESC_GPIO_RX(4),
|
FUNCTION_DESC_GPIO_RX(5),
|
FUNCTION_DESC_GPIO_RX(6),
|
FUNCTION_DESC_GPIO_RX(7),
|
FUNCTION_DESC_GPIO_RX(8),
|
FUNCTION_DESC_GPIO_RX(9),
|
FUNCTION_DESC_GPIO_RX(10),
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FUNCTION_DESC_GPIO_RX(11),
|
FUNCTION_DESC_GPIO_RX(12),
|
FUNCTION_DESC_GPIO_RX(13),
|
FUNCTION_DESC_GPIO_RX(14),
|
FUNCTION_DESC_GPIO_RX(15),
|
FUNCTION_DESC_GPIO_RX(16),
|
FUNCTION_DESC_GPIO_RX(17),
|
FUNCTION_DESC_GPIO_RX(18),
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FUNCTION_DESC_GPIO_RX(19),
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FUNCTION_DESC_GPIO_RX(20),
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FUNCTION_DESC_GPIO(),
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FUNCTION_DESC(I2C),
|
FUNCTION_DESC(UART),
|
};
|
|
static int max96755f_pinctrl_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct max96755f_pinctrl *mpctl;
|
struct pinctrl_desc *pctl_desc;
|
int i, ret;
|
|
mpctl = devm_kzalloc(dev, sizeof(*mpctl), GFP_KERNEL);
|
if (!mpctl)
|
return -ENOMEM;
|
|
mpctl->dev = dev;
|
platform_set_drvdata(pdev, mpctl);
|
|
mpctl->regmap = dev_get_regmap(dev->parent, NULL);
|
if (!mpctl->regmap)
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return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
|
|
pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
|
if (!pctl_desc)
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return -ENOMEM;
|
|
pctl_desc->name = dev_name(dev);
|
pctl_desc->owner = THIS_MODULE;
|
pctl_desc->pctlops = &max96755f_pinctrl_ops;
|
pctl_desc->pmxops = &max96755f_pinmux_ops;
|
pctl_desc->confops = &max96755f_pinconf_ops;
|
pctl_desc->pins = max96755f_pins_desc;
|
pctl_desc->npins = ARRAY_SIZE(max96755f_pins_desc);
|
|
ret = devm_pinctrl_register_and_init(dev, pctl_desc, mpctl,
|
&mpctl->pctl);
|
if (ret)
|
return dev_err_probe(dev, ret, "failed to register pinctrl\n");
|
|
for (i = 0; i < ARRAY_SIZE(max96755f_groups); i++) {
|
const struct group_desc *group = &max96755f_groups[i];
|
|
ret = pinctrl_generic_add_group(mpctl->pctl, group->name,
|
group->pins, group->num_pins,
|
group->data);
|
if (ret < 0)
|
return dev_err_probe(dev, ret,
|
"failed to register group %s\n",
|
group->name);
|
}
|
|
for (i = 0; i < ARRAY_SIZE(max96755f_functions); i++) {
|
const struct function_desc *func = &max96755f_functions[i];
|
|
ret = pinmux_generic_add_function(mpctl->pctl, func->name,
|
func->group_names,
|
func->num_group_names,
|
func->data);
|
if (ret < 0)
|
return dev_err_probe(dev, ret,
|
"failed to register function %s\n",
|
func->name);
|
}
|
|
return pinctrl_enable(mpctl->pctl);
|
}
|
|
static const struct of_device_id max96755f_pinctrl_of_match[] = {
|
{ .compatible = "maxim,max96755f-pinctrl" },
|
{}
|
};
|
MODULE_DEVICE_TABLE(of, max96755f_pinctrl_of_match);
|
|
static struct platform_driver max96755f_pinctrl_driver = {
|
.driver = {
|
.name = "max96755f-pinctrl",
|
.of_match_table = max96755f_pinctrl_of_match,
|
},
|
.probe = max96755f_pinctrl_probe,
|
};
|
|
module_platform_driver(max96755f_pinctrl_driver);
|
|
MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
|
MODULE_DESCRIPTION("Maxim max96755f pin control driver");
|
MODULE_LICENSE("GPL");
|
