// SPDX-License-Identifier: GPL-2.0
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/*
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* ACPI PCIe host controller driver for Rockchip SoCs
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*
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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* http://www.rock-chips.com
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*
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/pci-ecam.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci.h>
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#include "pcie-designware.h"
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#include "../../pci.h"
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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#define DWC_ATU_REGION_INDEX1 (0x1 << 0)
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#define ECAM_RESV_SIZE SZ_16M
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struct rk_pcie_acpi {
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void __iomem *dbi_base;
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void __iomem *cfg_base;
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phys_addr_t mcfg_addr;
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};
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static void rk_pcie_writel_ob_unroll(void __iomem *dbi_base, u32 index, u32 reg, u32 val)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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writel(val, dbi_base + offset + reg + DEFAULT_DBI_ATU_OFFSET);
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}
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static u32 rk_pcie_readl_ob_unroll(void __iomem *dbi_base, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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return readl(dbi_base + offset + reg + DEFAULT_DBI_ATU_OFFSET);
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}
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static void rk_pcie_prog_outbound_atu_unroll(struct device *dev, void __iomem *dbi_base, u32 index,
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u32 type, u64 cpu_addr, u64 pci_addr, u32 size)
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{
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u32 retries, val;
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dev_dbg(dev, "%s: ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
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__func__, index, type, cpu_addr, pci_addr, size);
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr));
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_UPPER_BASE, upper_32_bits(cpu_addr));
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_LOWER_LIMIT, lower_32_bits(cpu_addr + size - 1));
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_UPPER_LIMIT, upper_32_bits(cpu_addr + size - 1));
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(pci_addr));
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(pci_addr));
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_REGION_CTRL1, type);
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rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = rk_pcie_readl_ob_unroll(dbi_base, index, PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(dev, "outbound iATU is not being enabled\n");
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}
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static int rk_pcie_ecam_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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struct resource *res;
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phys_addr_t mcfg_addr;
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struct rk_pcie_acpi *rk_pcie;
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int ret;
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rk_pcie = devm_kzalloc(dev, sizeof(*rk_pcie), GFP_KERNEL);
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if (!rk_pcie)
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return -ENOMEM;
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/*
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* Retrieve RC base and size from a RKCP0001 device with _UID
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* matching our segment.
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*/
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res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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ret = acpi_get_rc_resources(dev, "RKCP0001", root->segment, res);
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if (ret) {
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dev_err(dev, "can't get rc base (DBI) address\n");
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return -ENOMEM;
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}
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dev_info(dev, "DBI address is %pa\n", &res->start);
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rk_pcie->dbi_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
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if (!rk_pcie->dbi_base)
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return -ENOMEM;
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mcfg_addr = acpi_pci_root_get_mcfg_addr(adev->handle);
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if (!mcfg_addr) {
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dev_err(dev, "can't get mcfg base (cfg) address\n");
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return -ENOMEM;
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}
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dev_info(dev, "mcfg address is %pa\n", &mcfg_addr);
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rk_pcie->mcfg_addr = mcfg_addr;
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rk_pcie->cfg_base = devm_pci_remap_cfgspace(dev, mcfg_addr, SZ_1M);
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if (!rk_pcie->cfg_base)
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return -ENOMEM;
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cfg->priv = rk_pcie;
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return 0;
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}
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static int rk_pcie_ecam_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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/* access only one slot on each root port */
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if (bus->number == cfg->busr.start && dev > 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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static int rk_pcie_ecam_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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/* access only one slot on each root port */
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if (bus->number == cfg->busr.start && dev > 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static void __iomem *rk_pcie_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
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{
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struct pci_config_window *cfg = bus->sysdata;
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struct rk_pcie_acpi *rk_pcie = cfg->priv;
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u32 atu_type;
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u32 busdev;
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/* read RC config space */
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if (bus->number == cfg->busr.start)
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return rk_pcie->dbi_base + where;
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if (pci_is_root_bus(bus->parent))
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atu_type = PCIE_ATU_TYPE_CFG0;
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else
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atu_type = PCIE_ATU_TYPE_CFG1;
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busdev = PCIE_ATU_BUS(bus->number) |
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PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
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/*
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* UEFI region mapping relation:
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* index0: 32-bit np memory
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* index1: config
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* index2: IO
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* index3: 64-bit np memory
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*/
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rk_pcie_prog_outbound_atu_unroll(cfg->parent, rk_pcie->dbi_base, DWC_ATU_REGION_INDEX1,
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atu_type, (u64)rk_pcie->mcfg_addr, busdev, ECAM_RESV_SIZE);
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dev_dbg(cfg->parent, "Read other config: 0x%p where = %d\n",
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rk_pcie->cfg_base + where, where);
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return rk_pcie->cfg_base + where;
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}
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const struct pci_ecam_ops rk_pcie_ecam_ops = {
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.bus_shift = 20, /* We don't need this */
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.init = rk_pcie_ecam_init,
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.pci_ops = {
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.map_bus = rk_pcie_ecam_map_bus,
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.read = rk_pcie_ecam_rd_conf,
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.write = rk_pcie_ecam_wr_conf,
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}
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};
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#endif
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