/*
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* Driver for Rockchip Smart Card Reader Controller
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*
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* Copyright (C) 2012-2016 ROCKCHIP, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __RK_SCR_H__
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#define __RK_SCR_H__
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/* CTRL1 bit fields */
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#define INVLEV BIT(0)
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#define INVORD BIT(1)
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#define PECH2FIFO BIT(2)
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#define CLKSTOP BIT(6)
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#define CLKSTOPVAL BIT(7)
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#define TXEN BIT(8)
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#define RXEN BIT(9)
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#define TS2FIFO BIT(10)
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#define T0T1 BIT(11)
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#define ATRSTFLUSH BIT(12)
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#define TCKEN BIT(13)
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#define GINTEN BIT(15)
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/* CTRL2 bit fields */
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#define WARMRST BIT(2)
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#define ACT BIT(3)
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#define DEACT BIT(4)
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#define VCC18 BIT(5)
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#define VCC33 BIT(6)
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#define VCC50 BIT(7)
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/* SCPADS bit fields */
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#define DIRACCPADS BIT(0)
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#define DSCIO BIT(1)
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#define DSCCLK BIT(2)
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#define DSCRST BIT(3)
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#define DSCVCC BIT(4)
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#define AUTOADEAVPP BIT(5)
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#define DSCVPPEN BIT(6)
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#define DSCVPPP BIT(7)
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#define DSCFCB BIT(8)
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#define SCPRESENT BIT(9)
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/* INTEN1 & INTSTAT1 bit fields */
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#define TXFIDONE BIT(0)
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#define TXFIEMPTY BIT(1)
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#define RXFIFULL BIT(2)
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#define CLKSTOPRUN BIT(3)
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#define TXDONE BIT(4)
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#define RXDONE BIT(5)
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#define TXPERR BIT(6)
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#define RXPERR BIT(7)
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#define C2CFULL BIT(8)
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#define RXTHRESHOLD BIT(9)
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#define ATRFAIL BIT(10)
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#define ATRDONE BIT(11)
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#define SCREM BIT(12)
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#define SCINS BIT(13)
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#define SCACT BIT(14)
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#define SCDEACT BIT(15)
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/* INTEN2 & INTSTAT2 bit fields */
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#define TXTHRESHOLD BIT(0)
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#define TCLKERR BIT(1)
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/* FIFOCTRL bit fields */
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#define FC_TXFIEMPTY BIT(0)
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#define FC_TXFIFULL BIT(1)
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#define FC_TXFIFLUSH BIT(2)
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#define FC_RXFIEMPTY BIT(8)
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#define FC_RXFIFULL BIT(9)
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#define FC_RXFIFLUSH BIT(10)
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/* FIFO_DEPTH must >= 2 */
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#define FIFO_DEPTH 32
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#define MAX_RXTHR (3 * FIFO_DEPTH / 4)
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#define MAX_TXTHR (256) /* at least, one less than FIFO_DEPTH */
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#define RK_SCR_NUM (2)
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#define SMC_ATR_MAX_LENGTH (512)
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#define SMC_ATR_MIN_LENGTH (2)
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#define SMC_SUCCESSFUL (0)
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#define SMC_ERROR_CARD_NOT_INSERT BIT(0)
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#define SMC_ERROR_NO_ANSWER BIT(1)
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#define SMC_ERROR_TX_ERR BIT(2)
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#define SMC_ERROR_RX_ERR BIT(3)
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#define SMC_ERROR_CONFLICT_ERR BIT(4)
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#define SMC_ERROR_WRITE_FULL_RECV_FIFO_ERR BIT(5)
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#define SMC_ERROR_BWT_ERR BIT(6)
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#define SMC_ERROR_CWT_ERR BIT(7)
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#define SMC_ERROR_BAD_PARAMETER BIT(8)
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#define SMC_ERROR_ATR_ERR BIT(9)
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#define SMC_ERROR_NO_MEMERY BIT(10)
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#define SMC_ERROR_TIMEOUT BIT(11)
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enum {
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SC_DRV_INT_CARDOUT = 0,
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SC_DRV_INT_CARDIN
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};
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/* card convention */
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enum {
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SC_CONV_DIRECT = 0,
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SC_CONV_INVERSE = 1
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};
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enum {
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SC_CARD_INDEX_0 = 0,
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SC_CARD_INDEX_1 = 1
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};
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/* card protocol */
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enum {
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SC_PROTOCOL_INVALID = -1,
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SC_PROTOCOL_T0 = 0,
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SC_PROTOCOL_T1 = 1,
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SC_PROTOCOL_T14 = 14
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};
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/* enumerated constants */
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enum status_code_e {
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SUCCESSFUL = 0, /* successful completion */
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TASK_EXITTED = 1, /* returned from a thread */
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MP_NOT_CONFIGURED = 2, /* multiprocessing not configured */
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INVALID_NAME = 3, /* invalid object name */
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INVALID_ID = 4, /* invalid object id */
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TOO_MANY = 5, /* too many */
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TIMEOUT = 6, /* timed out waiting */
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OBJECT_WAS_DELETED = 7, /* object deleted while waiting */
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INVALID_SIZE = 8, /* specified size was invalid */
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INVALID_ADDRESS = 9, /* address specified is invalid */
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INVALID_NUMBER = 10, /* number was invalid */
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NOT_DEFINED = 11, /* item has not been initialized */
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RESOURCE_IN_USE = 12, /* resources still outstanding */
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UNSATISFIED = 13, /* request not satisfied */
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INCORRECT_STATE = 14, /* thread is in wrong state */
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ALREADY_SUSPENDED = 15, /* thread already in state */
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ILLEGAL_ON_SELF = 16, /* illegal on calling thread */
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ILLEGAL_ON_REMOTE_OBJECT = 17, /* illegal for remote object */
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CALLED_FROM_ISR = 18, /* called from wrong environment */
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INVALID_PRIORITY = 19, /* invalid thread priority */
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INVALID_CLOCK = 20, /* invalid date/time */
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INVALID_NODE = 21, /* invalid node id */
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NOT_CONFIGURED = 22, /* directive not configured */
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NOT_OWNER_OF_RESOURCE = 23, /* not owner of resource */
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NOT_IMPLEMENTED = 24, /* directive not implemented */
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INTERNAL_ERROR = 25, /* inconsistency detected */
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NO_MEMORY = 26, /* could not get enough memory */
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IO_ERROR = 27, /* driver IO error */
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PROXY_BLOCKING = 28 /* internal error only */
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};
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struct scr_reg_t {
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unsigned int CTRL1; /* Control Reg 1 */
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unsigned int CTRL2; /* Control Reg 2 */
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unsigned int SCPADS; /* Direct access to Smart Card pads*/
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unsigned int INTEN1; /* Interrupt Enable Reg 1 */
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unsigned int INTSTAT1; /* Interrupt Status Reg 1 */
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unsigned int FIFOCTRL; /* FIFO control register */
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unsigned int LGCYCNT; /* Legacy TX & RX FIFO Counter */
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unsigned int RXFIFOTH; /* RXFIFO threshold */
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unsigned int REPEAT; /*
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* number of repeating after
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* unsuccessful transaction
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*/
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unsigned int CGSCDIV; /* SmartCard clock divisor */
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unsigned int CGBITDIV; /* Bit clock divisor */
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unsigned int SCGT; /* SmartCard GuardTime */
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unsigned int ADEATIME; /* Activation/deactivation time (cc)*/
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unsigned int LOWRSTTIME; /*
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* Duration of low state during
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* Smart Card reset sequence
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*/
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unsigned int ATRSTARTLIMIT; /* ATR start limit */
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unsigned int C2CLIM; /*
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* leading edge to leading edge of two
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* consecutive characters delay limit
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*/
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unsigned int INTEN2; /* Interrupt Enable Reg 2 */
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unsigned int INTSTAT2; /* Interrupt Status R */
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unsigned int TXFIFOTH; /* TXFIFO threshold */
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unsigned int TXFIFOCNT; /* TXFIFO counter */
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unsigned int RXFIFOCNT; /* RXFIFO counter */
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unsigned int CGBITTUNE; /* Bit tune register */
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unsigned int reserved[0x200 / 4];
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unsigned int FIFODATA; /*
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* FIFODATA space start
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* - RX FIFO and TX FIFO
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*/
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};
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enum hal_scr_id_e {
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HAL_SCR_ID0 = 0,
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HAL_SCR_ID1,
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HAL_SCR_ID_MAX
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};
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enum hal_scr_clock_stop_mode_e {
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/* Continuous clock mode, the autostop is disabled */
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HAL_SCR_CLOCK_NO_STOP,
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/* Automatic clock stop mode, stopped at low-level */
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HAL_SCR_CLOCK_STOP_L,
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/* Automatic clock stop mode, stopped at high-level */
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HAL_SCR_CLOCK_STOP_H
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};
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enum hal_scr_etu_duration_e {
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/* F and D to default value F=372, D=1 */
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HAL_SCR_ETU_F_372_AND_D_1,
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/* F=512 and D=8 */
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HAL_SCR_ETU_F_512_AND_D_8,
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/* F=512 and D=4 */
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HAL_SCR_ETU_F_512_AND_D_4
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};
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struct hal_scr_irq_status_t {
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/* When the reset time-outs. */
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unsigned char reset_timeout;
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/* When a parity error occurs. */
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unsigned char parity_error;
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/* When a bad ts character is received. */
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unsigned char bad_ts;
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/* When the auto-reset is successful. */
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unsigned char atr_success;
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/* When a rx transfer has been finished */
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unsigned char rx_success;
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/* When an auto-reset has been started. */
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unsigned char atr_start;
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/* When a work waiting time factor time-outs. */
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unsigned char wwt_timeout;
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/*
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* When the number of received character exceeds the
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* number of awaited bytes:1; (set in the SCI Rx counter register)
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*/
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unsigned char extra_rx;
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};
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/*check card is in or out*/
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enum hal_scr_detect_status_e {
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SMC_DRV_INT_CARDOUT = 0,
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SMC_DRV_INT_CARDIN
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};
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enum hal_scr_irq_cause_e {
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HAL_SCR_RESET_TIMEOUT,
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HAL_SCR_PARITY_ERROR,
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HAL_SCR_BAD_TS,
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HAL_SCR_ATR_SUCCESS,
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HAL_SCR_RX_SUCCESS,
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HAL_SCR_WWT_TIMEOUT,
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HAL_SCR_EXTRA_RX,
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HAL_SCR_IRQ_INVALID = 0x0fffffff
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};
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enum hal_scr_voltage_e {
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/* 5V */
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HAL_SCR_VOLTAGE_CLASS_A,
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/* 3V */
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HAL_SCR_VOLTAGE_CLASS_B,
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/* 1.8V */
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HAL_SCR_VOLTAGE_CLASS_C,
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/* 0V */
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HAL_SCR_VOLTAGE_NULL
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};
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/* card protocol */
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enum {
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SMC_PROTOCOL_INVALID = -1,
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SMC_PROTOCOL_T0 = 0,
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SMC_PROTOCOL_T1 = 1,
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SMC_PROTOCOL_T14 = 14
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};
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/* card convention */
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enum {
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SMC_CONV_DIRECT = 0,
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SMC_CONV_INVERSE = 1
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};
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/*card index*/
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enum {
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SMC_CARD_INDEX_0 = 0,
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SMC_CARD_INDEX_1 = 1
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};
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typedef void (*hal_scr_irq_handler_t) (enum hal_scr_irq_cause_e);
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struct scr_chip_info {
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struct scr_reg_t *reg_base;
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int irq;
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const char *clk_name;
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};
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struct rk_scr {
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const struct scr_chip_info *hw;
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struct clk *clk;
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hal_scr_irq_handler_t user_handler;
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struct hal_scr_irq_status_t user_mask;
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bool is_open;
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bool is_active;
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bool in_process;
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unsigned char *rx_buf;
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unsigned int rx_expected;
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unsigned int rx_cnt;
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const unsigned char *tx_buf;
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unsigned int tx_expected;
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unsigned int tx_cnt;
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unsigned int F;
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unsigned int D;
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struct notifier_block freq_changed_notifier;
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};
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#endif /* __RK_SCR_H__ */
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