/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <linux/arm-smccc.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/rockchip/rockchip_sip.h>
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#include <asm/cputype.h>
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#ifdef CONFIG_ARM
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#include <asm/psci.h>
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#endif
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#include <asm/smp_plat.h>
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#include <uapi/linux/psci.h>
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#include <linux/ptrace.h>
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#include <linux/sched/clock.h>
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#include <linux/slab.h>
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#include <soc/rockchip/rockchip_sip.h>
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#ifdef CONFIG_64BIT
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#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
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#else
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#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name
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#endif
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#define SIZE_PAGE(n) ((n) << 12)
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static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
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unsigned long arg0,
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unsigned long arg1,
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unsigned long arg2)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
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return res;
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}
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struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2)
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{
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return __invoke_sip_fn_smc(SIP_DRAM_CONFIG, arg0, arg1, arg2);
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}
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EXPORT_SYMBOL_GPL(sip_smc_dram);
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struct arm_smccc_res sip_smc_get_atf_version(void)
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{
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return __invoke_sip_fn_smc(SIP_ATF_VERSION, 0, 0, 0);
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}
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EXPORT_SYMBOL_GPL(sip_smc_get_atf_version);
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struct arm_smccc_res sip_smc_get_sip_version(void)
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{
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return __invoke_sip_fn_smc(SIP_SIP_VERSION, 0, 0, 0);
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}
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EXPORT_SYMBOL_GPL(sip_smc_get_sip_version);
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int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, ctrl, config1, config2);
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return res.a0;
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}
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EXPORT_SYMBOL_GPL(sip_smc_set_suspend_mode);
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struct arm_smccc_res sip_smc_get_suspend_info(u32 info)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, info, 0, 0);
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return res;
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}
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EXPORT_SYMBOL_GPL(sip_smc_get_suspend_info);
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int sip_smc_virtual_poweroff(void)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), 0, 0, 0);
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return res.a0;
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}
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EXPORT_SYMBOL_GPL(sip_smc_virtual_poweroff);
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int sip_smc_remotectl_config(u32 func, u32 data)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_REMOTECTL_CFG, func, data, 0);
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return res.a0;
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}
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EXPORT_SYMBOL_GPL(sip_smc_remotectl_config);
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u32 sip_smc_secure_reg_read(u32 addr_phy)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_ACCESS_REG, 0, addr_phy, SECURE_REG_RD);
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if (res.a0)
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pr_err("%s error: %d, addr phy: 0x%x\n",
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__func__, (int)res.a0, addr_phy);
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return res.a1;
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}
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EXPORT_SYMBOL_GPL(sip_smc_secure_reg_read);
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int sip_smc_secure_reg_write(u32 addr_phy, u32 val)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_ACCESS_REG, val, addr_phy, SECURE_REG_WR);
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if (res.a0)
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pr_err("%s error: %d, addr phy: 0x%x\n",
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__func__, (int)res.a0, addr_phy);
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return res.a0;
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}
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EXPORT_SYMBOL_GPL(sip_smc_secure_reg_write);
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static void *sip_map(phys_addr_t start, size_t size)
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{
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struct page **pages;
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phys_addr_t page_start;
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unsigned int page_count;
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pgprot_t prot;
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unsigned int i;
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void *vaddr;
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if (!pfn_valid(__phys_to_pfn(start)))
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return ioremap(start, size);
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page_start = start - offset_in_page(start);
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page_count = DIV_ROUND_UP(size + offset_in_page(start), PAGE_SIZE);
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prot = pgprot_noncached(PAGE_KERNEL);
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pages = kmalloc_array(page_count, sizeof(struct page *), GFP_KERNEL);
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if (!pages) {
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pr_err("%s: Failed to allocate array for %u pages\n",
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__func__, page_count);
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return NULL;
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}
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for (i = 0; i < page_count; i++)
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pages[i] = phys_to_page(page_start + i * PAGE_SIZE);
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vaddr = vmap(pages, page_count, VM_MAP, prot);
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kfree(pages);
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/*
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* Since vmap() uses page granularity, we must add the offset
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* into the page here, to get the byte granularity address
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* into the mapping to represent the actual "start" location.
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*/
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return vaddr + offset_in_page(start);
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}
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struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
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share_page_type_t page_type)
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{
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struct arm_smccc_res res;
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unsigned long share_mem_phy;
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res = __invoke_sip_fn_smc(SIP_SHARE_MEM, page_num, page_type, 0);
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if (IS_SIP_ERROR(res.a0))
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goto error;
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share_mem_phy = res.a1;
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res.a1 = (unsigned long)sip_map(share_mem_phy, SIZE_PAGE(page_num));
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error:
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return res;
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}
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EXPORT_SYMBOL_GPL(sip_smc_request_share_mem);
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struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2)
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{
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return __invoke_sip_fn_smc(SIP_MCU_EL3FIQ_CFG, arg0, arg1, arg2);
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}
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EXPORT_SYMBOL_GPL(sip_smc_mcu_el3fiq);
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struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(PSCI_SIP_VPU_RESET, arg0, arg1, arg2);
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return res;
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}
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EXPORT_SYMBOL_GPL(sip_smc_vpu_reset);
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struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_BUS_CFG, arg0, arg1, arg2);
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return res;
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}
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EXPORT_SYMBOL_GPL(sip_smc_bus_config);
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struct dram_addrmap_info *sip_smc_get_dram_map(void)
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{
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struct arm_smccc_res res;
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static struct dram_addrmap_info *map;
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if (map)
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return map;
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/* Request share memory size 4KB */
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res = sip_smc_request_share_mem(1, SHARE_PAGE_TYPE_DDR_ADDRMAP);
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if (res.a0 != 0) {
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pr_err("no ATF memory for init\n");
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return NULL;
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}
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map = (struct dram_addrmap_info *)res.a1;
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res = sip_smc_dram(SHARE_PAGE_TYPE_DDR_ADDRMAP, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_ADDRMAP_GET);
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if (res.a0) {
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pr_err("rockchip_sip_config_dram_init error:%lx\n", res.a0);
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map = NULL;
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return NULL;
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}
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return map;
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}
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EXPORT_SYMBOL_GPL(sip_smc_get_dram_map);
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struct arm_smccc_res sip_smc_lastlog_request(void)
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{
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struct arm_smccc_res res;
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void __iomem *addr1, *addr2;
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res = __invoke_sip_fn_smc(SIP_LAST_LOG, local_clock(), 0, 0);
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if (IS_SIP_ERROR(res.a0))
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return res;
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addr1 = sip_map(res.a1, res.a3);
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if (!addr1) {
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pr_err("%s: share memory buffer0 ioremap failed\n", __func__);
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res.a0 = SIP_RET_INVALID_ADDRESS;
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return res;
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}
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addr2 = sip_map(res.a2, res.a3);
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if (!addr2) {
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pr_err("%s: share memory buffer1 ioremap failed\n", __func__);
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res.a0 = SIP_RET_INVALID_ADDRESS;
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return res;
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}
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res.a1 = (unsigned long)addr1;
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res.a2 = (unsigned long)addr2;
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return res;
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}
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EXPORT_SYMBOL_GPL(sip_smc_lastlog_request);
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int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(RK_SIP_AMP_CFG, sub_func_id, arg1, arg2, arg3,
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0, 0, 0, &res);
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return res.a0;
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}
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EXPORT_SYMBOL_GPL(sip_smc_amp_config);
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struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id, u32 arg1)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(RK_SIP_AMP_CFG, sub_func_id, arg1, 0, 0, 0, 0, 0, &res);
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return res;
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}
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EXPORT_SYMBOL_GPL(sip_smc_get_amp_info);
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void __iomem *sip_hdcp_request_share_memory(int id)
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{
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static void __iomem *base;
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struct arm_smccc_res res;
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if (id < 0 || id >= MAX_DEVICE) {
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pr_err("%s: invalid device id\n", __func__);
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return NULL;
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}
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if (!base) {
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/* request page share memory */
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res = sip_smc_request_share_mem(2, SHARE_PAGE_TYPE_HDCP);
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if (IS_SIP_ERROR(res.a0))
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return NULL;
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base = (void __iomem *)res.a1;
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}
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return base + id * 1024;
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}
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EXPORT_SYMBOL_GPL(sip_hdcp_request_share_memory);
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struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_HDCP_CONFIG, arg0, arg1, arg2);
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return res;
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}
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EXPORT_SYMBOL_GPL(sip_hdcp_config);
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/************************** fiq debugger **************************************/
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/*
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* AArch32 is not allowed to call SMC64(ATF framework does not support), so we
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* don't change SIP_UARTDBG_FN to SIP_UARTDBG_CFG64 even when cpu is AArch32
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* mode. Let ATF support SIP_UARTDBG_CFG, and we just initialize SIP_UARTDBG_FN
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* depends on compile option(CONFIG_ARM or CONFIG_ARM64).
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*/
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#ifdef CONFIG_ARM64
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#define SIP_UARTDBG_FN SIP_UARTDBG_CFG64
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#else
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#define SIP_UARTDBG_FN SIP_UARTDBG_CFG
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static int firmware_64_32bit;
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#endif
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static int fiq_sip_enabled;
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static int fiq_target_cpu;
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static phys_addr_t ft_fiq_mem_phy;
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static void __iomem *ft_fiq_mem_base;
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static sip_fiq_debugger_uart_irq_tf_cb_t sip_fiq_debugger_uart_irq_tf;
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static struct pt_regs fiq_pt_regs;
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int sip_fiq_debugger_is_enabled(void)
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{
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return fiq_sip_enabled;
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}
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EXPORT_SYMBOL_GPL(sip_fiq_debugger_is_enabled);
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static void sip_fiq_debugger_get_pt_regs(void *reg_base,
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unsigned long sp_el1)
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{
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__maybe_unused struct sm_nsec_ctx *nsec_ctx = reg_base;
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__maybe_unused struct gp_regs_ctx *gp_regs = reg_base;
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#ifdef CONFIG_ARM64
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/*
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* 64-bit ATF + 64-bit kernel
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*/
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/* copy cpu context: x0 ~ spsr_el3 */
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memcpy(&fiq_pt_regs, reg_base, 8 * 31);
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/* copy pstate: spsr_el3 */
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memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
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fiq_pt_regs.sp = sp_el1;
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/* copy pc: elr_el3 */
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memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
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#else
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if (firmware_64_32bit == FIRMWARE_ATF_64BIT) {
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/*
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* 64-bit ATF + 32-bit kernel
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*/
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fiq_pt_regs.ARM_r0 = gp_regs->x0;
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fiq_pt_regs.ARM_r1 = gp_regs->x1;
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fiq_pt_regs.ARM_r2 = gp_regs->x2;
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fiq_pt_regs.ARM_r3 = gp_regs->x3;
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fiq_pt_regs.ARM_r4 = gp_regs->x4;
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fiq_pt_regs.ARM_r5 = gp_regs->x5;
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fiq_pt_regs.ARM_r6 = gp_regs->x6;
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fiq_pt_regs.ARM_r7 = gp_regs->x7;
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fiq_pt_regs.ARM_r8 = gp_regs->x8;
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fiq_pt_regs.ARM_r9 = gp_regs->x9;
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fiq_pt_regs.ARM_r10 = gp_regs->x10;
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fiq_pt_regs.ARM_fp = gp_regs->x11;
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fiq_pt_regs.ARM_ip = gp_regs->x12;
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fiq_pt_regs.ARM_sp = gp_regs->x19; /* aarch32 svc_r13 */
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fiq_pt_regs.ARM_lr = gp_regs->x18; /* aarch32 svc_r14 */
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fiq_pt_regs.ARM_cpsr = gp_regs->spsr_el3;
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fiq_pt_regs.ARM_pc = gp_regs->elr_el3;
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} else {
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/*
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* 32-bit tee firmware + 32-bit kernel
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*/
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fiq_pt_regs.ARM_r0 = nsec_ctx->r0;
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fiq_pt_regs.ARM_r1 = nsec_ctx->r1;
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fiq_pt_regs.ARM_r2 = nsec_ctx->r2;
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fiq_pt_regs.ARM_r3 = nsec_ctx->r3;
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fiq_pt_regs.ARM_r4 = nsec_ctx->r4;
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fiq_pt_regs.ARM_r5 = nsec_ctx->r5;
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fiq_pt_regs.ARM_r6 = nsec_ctx->r6;
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fiq_pt_regs.ARM_r7 = nsec_ctx->r7;
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fiq_pt_regs.ARM_r8 = nsec_ctx->r8;
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fiq_pt_regs.ARM_r9 = nsec_ctx->r9;
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fiq_pt_regs.ARM_r10 = nsec_ctx->r10;
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fiq_pt_regs.ARM_fp = nsec_ctx->r11;
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fiq_pt_regs.ARM_ip = nsec_ctx->r12;
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fiq_pt_regs.ARM_sp = nsec_ctx->svc_sp;
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fiq_pt_regs.ARM_lr = nsec_ctx->svc_lr;
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fiq_pt_regs.ARM_cpsr = nsec_ctx->mon_spsr;
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/*
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* 'nsec_ctx->mon_lr' is not the fiq break point's PC, because it will
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* be override as 'psci_fiq_debugger_uart_irq_tf_cb' for optee-os to
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* jump to fiq_debugger handler.
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*
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* As 'nsec_ctx->und_lr' is not used for kernel, so optee-os uses it to
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* deliver fiq break point's PC.
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*
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*/
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fiq_pt_regs.ARM_pc = nsec_ctx->und_lr;
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}
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#endif
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}
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static void sip_fiq_debugger_uart_irq_tf_cb(unsigned long sp_el1,
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unsigned long offset,
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unsigned long cpu)
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{
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char *cpu_context;
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/* calling fiq handler */
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if (ft_fiq_mem_base) {
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cpu_context = (char *)ft_fiq_mem_base + offset;
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sip_fiq_debugger_get_pt_regs(cpu_context, sp_el1);
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sip_fiq_debugger_uart_irq_tf(&fiq_pt_regs, cpu);
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}
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/* fiq handler done, return to EL3(then EL3 return to EL1 entry) */
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__invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, UARTDBG_CFG_OSHDL_TO_OS);
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}
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int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, sip_fiq_debugger_uart_irq_tf_cb_t callback_fn)
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{
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struct arm_smccc_res res;
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fiq_target_cpu = 0;
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/* init fiq debugger callback */
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sip_fiq_debugger_uart_irq_tf = callback_fn;
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res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, irq_id,
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(unsigned long)sip_fiq_debugger_uart_irq_tf_cb,
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UARTDBG_CFG_INIT);
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if (IS_SIP_ERROR(res.a0)) {
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pr_err("%s error: %d\n", __func__, (int)res.a0);
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return res.a0;
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}
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/* share memory ioremap */
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if (!ft_fiq_mem_base) {
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ft_fiq_mem_phy = res.a1;
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ft_fiq_mem_base = sip_map(ft_fiq_mem_phy,
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FIQ_UARTDBG_SHARE_MEM_SIZE);
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if (!ft_fiq_mem_base) {
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pr_err("%s: share memory ioremap failed\n", __func__);
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return -ENOMEM;
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}
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}
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fiq_sip_enabled = 1;
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return SIP_RET_SUCCESS;
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}
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EXPORT_SYMBOL_GPL(sip_fiq_debugger_uart_irq_tf_init);
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static ulong cpu_logical_map_mpidr(u32 cpu)
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{
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#ifdef MODULE
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/* Empirically, local "cpu_logical_map()" for rockchip platforms */
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ulong mpidr = read_cpuid_mpidr();
|
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if (mpidr & MPIDR_MT_BITMASK) {
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/* 0x100, 0x200, 0x300, 0x400 ... */
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mpidr = (cpu & 0xff) << 8;
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} else {
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if (cpu < 4)
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/* 0x00, 0x01, 0x02, 0x03 */
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mpidr = cpu;
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else if (cpu < 8)
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/* 0x100, 0x101, 0x102, 0x103 */
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mpidr = 0x100 | (cpu - 4);
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else
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pr_err("Unsupported map cpu: %d\n", cpu);
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}
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return mpidr;
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#else
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return cpu_logical_map(cpu);
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#endif
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}
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ulong sip_cpu_logical_map_mpidr(u32 cpu)
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{
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return cpu_logical_map_mpidr(cpu);
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}
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EXPORT_SYMBOL_GPL(sip_cpu_logical_map_mpidr);
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int sip_fiq_debugger_switch_cpu(u32 cpu)
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{
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struct arm_smccc_res res;
|
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fiq_target_cpu = cpu;
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res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, cpu_logical_map_mpidr(cpu),
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0, UARTDBG_CFG_OSHDL_CPUSW);
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return res.a0;
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}
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int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu, u32 flag)
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{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_SDEI_FIQ_DBG_SWITCH_CPU,
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cur_cpu, target_cpu, flag);
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return res.a0;
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}
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int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag)
|
{
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struct arm_smccc_res res;
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res = __invoke_sip_fn_smc(SIP_SDEI_FIQ_DBG_GET_EVENT_ID,
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0, 0, 0);
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*fiq = res.a1;
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*sw_cpu = res.a2;
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if (flag)
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*flag = res.a3;
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return res.a0;
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}
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EXPORT_SYMBOL_GPL(sip_fiq_debugger_switch_cpu);
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void sip_fiq_debugger_enable_debug(bool enable)
|
{
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unsigned long val;
|
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val = enable ? UARTDBG_CFG_OSHDL_DEBUG_ENABLE :
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UARTDBG_CFG_OSHDL_DEBUG_DISABLE;
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__invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, val);
|
}
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EXPORT_SYMBOL_GPL(sip_fiq_debugger_enable_debug);
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int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate)
|
{
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struct arm_smccc_res res;
|
|
res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, port_phyaddr, baudrate,
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UARTDBG_CFG_PRINT_PORT);
|
return res.a0;
|
}
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EXPORT_SYMBOL_GPL(sip_fiq_debugger_set_print_port);
|
|
int sip_fiq_debugger_request_share_memory(void)
|
{
|
struct arm_smccc_res res;
|
|
/* request page share memory */
|
res = sip_smc_request_share_mem(FIQ_UARTDBG_PAGE_NUMS,
|
SHARE_PAGE_TYPE_UARTDBG);
|
if (IS_SIP_ERROR(res.a0))
|
return res.a0;
|
|
return SIP_RET_SUCCESS;
|
}
|
EXPORT_SYMBOL_GPL(sip_fiq_debugger_request_share_memory);
|
|
int sip_fiq_debugger_get_target_cpu(void)
|
{
|
return fiq_target_cpu;
|
}
|
EXPORT_SYMBOL_GPL(sip_fiq_debugger_get_target_cpu);
|
|
void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu)
|
{
|
u32 en;
|
|
fiq_target_cpu = tgt_cpu;
|
en = enable ? UARTDBG_CFG_FIQ_ENABEL : UARTDBG_CFG_FIQ_DISABEL;
|
__invoke_sip_fn_smc(SIP_UARTDBG_FN, tgt_cpu, 0, en);
|
}
|
EXPORT_SYMBOL_GPL(sip_fiq_debugger_enable_fiq);
|
|
int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data)
|
{
|
struct arm_smccc_res res;
|
|
res = __invoke_sip_fn_smc(RK_SIP_FIQ_CTRL,
|
sub_func, irq, data);
|
return res.a0;
|
}
|
EXPORT_SYMBOL_GPL(sip_fiq_control);
|
|
int sip_wdt_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3)
|
{
|
struct arm_smccc_res res;
|
|
arm_smccc_smc(SIP_WDT_CFG, sub_func, arg1, arg2, arg3,
|
0, 0, 0, &res);
|
|
return res.a0;
|
}
|
EXPORT_SYMBOL_GPL(sip_wdt_config);
|
|
int sip_hdmirx_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3)
|
{
|
struct arm_smccc_res res;
|
|
arm_smccc_smc(SIP_HDMIRX_CFG, sub_func, arg1, arg2, arg3,
|
0, 0, 0, &res);
|
|
return res.a0;
|
}
|
EXPORT_SYMBOL_GPL(sip_hdmirx_config);
|
|
int sip_hdcpkey_init(u32 hdcp_id)
|
{
|
struct arm_smccc_res res;
|
|
res = __invoke_sip_fn_smc(TRUSTED_OS_HDCPKEY_INIT, hdcp_id, 0, 0);
|
|
return res.a0;
|
}
|
EXPORT_SYMBOL_GPL(sip_hdcpkey_init);
|
|
int sip_smc_mcu_config(unsigned long mcu_id,
|
unsigned long func,
|
unsigned long arg2)
|
{
|
struct arm_smccc_res res;
|
|
res = __invoke_sip_fn_smc(SIP_MCU_CFG, mcu_id, func, arg2);
|
return res.a0;
|
}
|
EXPORT_SYMBOL_GPL(sip_smc_mcu_config);
|
/******************************************************************************/
|
#ifdef CONFIG_ARM
|
static __init int sip_firmware_init(void)
|
{
|
struct arm_smccc_res res;
|
|
if (!psci_smp_available())
|
return 0;
|
|
/*
|
* OP-TEE works on kernel 3.10 and 4.4 and we have different sip
|
* implement. We should tell OP-TEE the current rockchip sip version.
|
*/
|
res = __invoke_sip_fn_smc(SIP_SIP_VERSION, SIP_IMPLEMENT_V2,
|
SECURE_REG_WR, 0);
|
if (IS_SIP_ERROR(res.a0))
|
pr_err("%s: set rockchip sip version v2 failed\n", __func__);
|
|
/*
|
* Currently, we support:
|
*
|
* 1. 64-bit ATF + 64-bit kernel;
|
* 2. 64-bit ATF + 32-bit kernel;
|
* 3. 32-bit TEE + 32-bit kernel;
|
*
|
* We need to detect which case of above and record in firmware_64_32bit
|
* We get info from cpuid and compare with all supported ARMv7 cpu.
|
*/
|
switch (read_cpuid_part()) {
|
case ARM_CPU_PART_CORTEX_A7:
|
case ARM_CPU_PART_CORTEX_A8:
|
case ARM_CPU_PART_CORTEX_A9:
|
case ARM_CPU_PART_CORTEX_A12:
|
case ARM_CPU_PART_CORTEX_A15:
|
case ARM_CPU_PART_CORTEX_A17:
|
firmware_64_32bit = FIRMWARE_TEE_32BIT;
|
break;
|
default:
|
firmware_64_32bit = FIRMWARE_ATF_64BIT;
|
break;
|
}
|
|
return 0;
|
}
|
arch_initcall(sip_firmware_init);
|
#endif
|
|
MODULE_DESCRIPTION("Rockchip SIP Call");
|
MODULE_LICENSE("GPL");
|
