/*
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* arch/xtensa/kernel/head.S
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*
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* Xtensa Processor startup code.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2008 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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* Kevin Chea
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cacheasm.h>
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#include <asm/initialize_mmu.h>
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#include <asm/mxregs.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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/*
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* This module contains the entry code for kernel images. It performs the
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* minimal setup needed to call the generic C routines.
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*
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* Prerequisites:
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*
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* - The kernel image has been loaded to the actual address where it was
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* compiled to.
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* - a2 contains either 0 or a pointer to a list of boot parameters.
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* (see setup.c for more details)
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*
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*/
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/*
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* _start
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*
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* The bootloader passes a pointer to a list of boot parameters in a2.
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*/
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/* The first bytes of the kernel image must be an instruction, so we
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* manually allocate and define the literal constant we need for a jx
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* instruction.
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*/
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__HEAD
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.begin no-absolute-literals
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ENTRY(_start)
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/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
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wsr a2, excsave1
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_j _SetupOCD
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.align 4
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.literal_position
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_SetupOCD:
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/*
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* Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
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* Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
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* xt-gdb to single step via DEBUG exceptions received directly
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* by ocd.
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*/
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movi a1, 1
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movi a0, 0
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wsr a1, windowstart
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wsr a0, windowbase
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rsync
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movi a1, LOCKLEVEL
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wsr a1, ps
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rsync
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.global _SetupMMU
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_SetupMMU:
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Offset = _SetupMMU - _start
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#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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initialize_mmu
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#if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
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rsr a2, excsave1
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movi a3, XCHAL_KSEG_PADDR
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bltu a2, a3, 1f
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sub a2, a2, a3
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movi a3, XCHAL_KSEG_SIZE
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bgeu a2, a3, 1f
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movi a3, XCHAL_KSEG_CACHED_VADDR
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add a2, a2, a3
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wsr a2, excsave1
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1:
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#endif
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#endif
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movi a0, _startup
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jx a0
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ENDPROC(_start)
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.end no-absolute-literals
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__REF
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.literal_position
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ENTRY(_startup)
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/* Set a0 to 0 for the remaining initialization. */
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movi a0, 0
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#if XCHAL_HAVE_VECBASE
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movi a2, VECBASE_VADDR
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wsr a2, vecbase
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#endif
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/* Clear debugging registers. */
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#if XCHAL_HAVE_DEBUG
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#if XCHAL_NUM_IBREAK > 0
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wsr a0, ibreakenable
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#endif
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wsr a0, icount
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movi a1, 15
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wsr a0, icountlevel
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.set _index, 0
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.rept XCHAL_NUM_DBREAK
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wsr a0, SREG_DBREAKC + _index
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.set _index, _index + 1
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.endr
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#endif
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/* Clear CCOUNT (not really necessary, but nice) */
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wsr a0, ccount # not really necessary, but nice
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/* Disable zero-loops. */
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#if XCHAL_HAVE_LOOPS
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wsr a0, lcount
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#endif
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/* Disable all timers. */
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.set _index, 0
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.rept XCHAL_NUM_TIMERS
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wsr a0, SREG_CCOMPARE + _index
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.set _index, _index + 1
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.endr
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/* Interrupt initialization. */
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movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
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wsr a0, intenable
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wsr a2, intclear
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/* Disable coprocessors. */
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#if XCHAL_HAVE_CP
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wsr a0, cpenable
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#endif
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/* Initialize the caches.
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* a2, a3 are just working registers (clobbered).
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*/
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#if XCHAL_DCACHE_LINE_LOCKABLE
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___unlock_dcache_all a2 a3
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#endif
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#if XCHAL_ICACHE_LINE_LOCKABLE
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___unlock_icache_all a2 a3
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#endif
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___invalidate_dcache_all a2 a3
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___invalidate_icache_all a2 a3
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isync
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initialize_cacheattr
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#ifdef CONFIG_HAVE_SMP
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movi a2, CCON # MX External Register to Configure Cache
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movi a3, 1
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wer a3, a2
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#endif
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/* Setup stack and enable window exceptions (keep irqs disabled) */
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movi a1, start_info
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l32i a1, a1, 0
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movi a2, PS_WOE_MASK | LOCKLEVEL
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# WOE=1, INTLEVEL=LOCKLEVEL, UM=0
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wsr a2, ps # (enable reg-windows; progmode stack)
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rsync
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#ifdef CONFIG_SMP
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/*
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* Notice that we assume with SMP that cores have PRID
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* supported by the cores.
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*/
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rsr a2, prid
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bnez a2, .Lboot_secondary
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#endif /* CONFIG_SMP */
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/* Unpack data sections
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*
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* The linker script used to build the Linux kernel image
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* creates a table located at __boot_reloc_table_start
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* that contans the information what data needs to be unpacked.
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*
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* Uses a2-a7.
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*/
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movi a2, __boot_reloc_table_start
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movi a3, __boot_reloc_table_end
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1: beq a2, a3, 3f # no more entries?
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l32i a4, a2, 0 # start destination (in RAM)
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l32i a5, a2, 4 # end desination (in RAM)
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l32i a6, a2, 8 # start source (in ROM)
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addi a2, a2, 12 # next entry
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beq a4, a5, 1b # skip, empty entry
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beq a4, a6, 1b # skip, source and dest. are the same
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2: l32i a7, a6, 0 # load word
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addi a6, a6, 4
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s32i a7, a4, 0 # store word
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addi a4, a4, 4
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bltu a4, a5, 2b
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j 1b
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3:
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/* All code and initialized data segments have been copied.
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* Now clear the BSS segment.
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*/
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movi a2, __bss_start # start of BSS
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movi a3, __bss_stop # end of BSS
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__loopt a2, a3, a4, 2
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s32i a0, a2, 0
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__endla a2, a3, 4
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#if XCHAL_DCACHE_IS_WRITEBACK
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/* After unpacking, flush the writeback cache to memory so the
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* instructions/data are available.
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*/
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___flush_dcache_all a2 a3
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#endif
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memw
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isync
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___invalidate_icache_all a2 a3
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isync
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#ifdef CONFIG_XIP_KERNEL
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/* Setup bootstrap CPU stack in XIP kernel */
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movi a1, start_info
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l32i a1, a1, 0
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#endif
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movi a6, 0
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xsr a6, excsave1
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/* init_arch kick-starts the linux kernel */
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call4 init_arch
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call4 start_kernel
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should_never_return:
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j should_never_return
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#ifdef CONFIG_SMP
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.Lboot_secondary:
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movi a2, cpu_start_ccount
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1:
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memw
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l32i a3, a2, 0
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beqi a3, 0, 1b
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movi a3, 0
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s32i a3, a2, 0
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1:
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memw
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l32i a3, a2, 0
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beqi a3, 0, 1b
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wsr a3, ccount
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movi a3, 0
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s32i a3, a2, 0
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memw
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movi a6, 0
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wsr a6, excsave1
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call4 secondary_start_kernel
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j should_never_return
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#endif /* CONFIG_SMP */
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ENDPROC(_startup)
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#ifdef CONFIG_HOTPLUG_CPU
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ENTRY(cpu_restart)
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#if XCHAL_DCACHE_IS_WRITEBACK
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___flush_invalidate_dcache_all a2 a3
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#else
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___invalidate_dcache_all a2 a3
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#endif
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memw
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movi a2, CCON # MX External Register to Configure Cache
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movi a3, 0
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wer a3, a2
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extw
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rsr a0, prid
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neg a2, a0
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movi a3, cpu_start_id
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memw
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s32i a2, a3, 0
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#if XCHAL_DCACHE_IS_WRITEBACK
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dhwbi a3, 0
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#endif
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1:
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memw
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l32i a2, a3, 0
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dhi a3, 0
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bne a2, a0, 1b
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/*
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* Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
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* Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
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* xt-gdb to single step via DEBUG exceptions received directly
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* by ocd.
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*/
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movi a1, 1
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movi a0, 0
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wsr a1, windowstart
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wsr a0, windowbase
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rsync
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movi a1, LOCKLEVEL
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wsr a1, ps
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rsync
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j _startup
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ENDPROC(cpu_restart)
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#endif /* CONFIG_HOTPLUG_CPU */
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/*
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* DATA section
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*/
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__REFDATA
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.align 4
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ENTRY(start_info)
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.long init_thread_union + KERNEL_STACK_SIZE
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/*
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* BSS section
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*/
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__PAGE_ALIGNED_BSS
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#ifdef CONFIG_MMU
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ENTRY(swapper_pg_dir)
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.fill PAGE_SIZE, 1, 0
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END(swapper_pg_dir)
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#endif
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ENTRY(empty_zero_page)
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.fill PAGE_SIZE, 1, 0
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END(empty_zero_page)
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