/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* verify_cpu.S - Code for cpu long mode and SSE verification. This
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* code has been borrowed from boot/setup.S and was introduced by
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* Andi Kleen.
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*
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* Copyright (c) 2007 Andi Kleen (ak@suse.de)
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* Copyright (c) 2007 Eric Biederman (ebiederm@xmission.com)
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* Copyright (c) 2007 Vivek Goyal (vgoyal@in.ibm.com)
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* Copyright (c) 2010 Kees Cook (kees.cook@canonical.com)
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*
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* This is a common code for verification whether CPU supports
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* long mode and SSE or not. It is not called directly instead this
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* file is included at various places and compiled in that context.
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* This file is expected to run in 32bit code. Currently:
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*
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* arch/x86/boot/compressed/head_64.S: Boot cpu verification
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* arch/x86/kernel/trampoline_64.S: secondary processor verification
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* arch/x86/kernel/head_32.S: processor startup
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*
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* verify_cpu, returns the status of longmode and SSE in register %eax.
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* 0: Success 1: Failure
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*
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* On Intel, the XD_DISABLE flag will be cleared as a side-effect.
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*
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* The caller needs to check for the error code and take the action
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* appropriately. Either display a message or halt.
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*/
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#include <asm/cpufeatures.h>
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#include <asm/msr-index.h>
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SYM_FUNC_START_LOCAL(verify_cpu)
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pushf # Save caller passed flags
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push $0 # Kill any dangerous flags
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popf
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#ifndef __x86_64__
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pushfl # standard way to check for cpuid
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popl %eax
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movl %eax,%ebx
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xorl $0x200000,%eax
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pushl %eax
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popfl
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pushfl
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popl %eax
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cmpl %eax,%ebx
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jz .Lverify_cpu_no_longmode # cpu has no cpuid
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#endif
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movl $0x0,%eax # See if cpuid 1 is implemented
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cpuid
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cmpl $0x1,%eax
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jb .Lverify_cpu_no_longmode # no cpuid 1
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xor %di,%di
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cmpl $0x68747541,%ebx # AuthenticAMD
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jnz .Lverify_cpu_noamd
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cmpl $0x69746e65,%edx
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jnz .Lverify_cpu_noamd
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cmpl $0x444d4163,%ecx
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jnz .Lverify_cpu_noamd
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mov $1,%di # cpu is from AMD
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jmp .Lverify_cpu_check
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.Lverify_cpu_noamd:
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cmpl $0x756e6547,%ebx # GenuineIntel?
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jnz .Lverify_cpu_check
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cmpl $0x49656e69,%edx
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jnz .Lverify_cpu_check
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cmpl $0x6c65746e,%ecx
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jnz .Lverify_cpu_check
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# only call IA32_MISC_ENABLE when:
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# family > 6 || (family == 6 && model >= 0xd)
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movl $0x1, %eax # check CPU family and model
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cpuid
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movl %eax, %ecx
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andl $0x0ff00f00, %eax # mask family and extended family
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shrl $8, %eax
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cmpl $6, %eax
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ja .Lverify_cpu_clear_xd # family > 6, ok
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jb .Lverify_cpu_check # family < 6, skip
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andl $0x000f00f0, %ecx # mask model and extended model
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shrl $4, %ecx
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cmpl $0xd, %ecx
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jb .Lverify_cpu_check # family == 6, model < 0xd, skip
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.Lverify_cpu_clear_xd:
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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btrl $2, %edx # clear MSR_IA32_MISC_ENABLE_XD_DISABLE
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jnc .Lverify_cpu_check # only write MSR if bit was changed
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wrmsr
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.Lverify_cpu_check:
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movl $0x1,%eax # Does the cpu have what it takes
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cpuid
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andl $REQUIRED_MASK0,%edx
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xorl $REQUIRED_MASK0,%edx
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jnz .Lverify_cpu_no_longmode
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movl $0x80000000,%eax # See if extended cpuid is implemented
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cpuid
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cmpl $0x80000001,%eax
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jb .Lverify_cpu_no_longmode # no extended cpuid
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movl $0x80000001,%eax # Does the cpu have what it takes
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cpuid
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andl $REQUIRED_MASK1,%edx
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xorl $REQUIRED_MASK1,%edx
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jnz .Lverify_cpu_no_longmode
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.Lverify_cpu_sse_test:
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movl $1,%eax
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cpuid
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andl $SSE_MASK,%edx
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cmpl $SSE_MASK,%edx
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je .Lverify_cpu_sse_ok
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test %di,%di
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jz .Lverify_cpu_no_longmode # only try to force SSE on AMD
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movl $MSR_K7_HWCR,%ecx
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rdmsr
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btr $15,%eax # enable SSE
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wrmsr
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xor %di,%di # don't loop
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jmp .Lverify_cpu_sse_test # try again
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.Lverify_cpu_no_longmode:
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popf # Restore caller passed flags
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movl $1,%eax
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RET
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.Lverify_cpu_sse_ok:
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popf # Restore caller passed flags
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xorl %eax, %eax
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RET
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SYM_FUNC_END(verify_cpu)
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