/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __UM_CACHE_H
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#define __UM_CACHE_H
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#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
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# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
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#elif defined(CONFIG_UML_X86) /* 64-bit */
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# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */
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#else
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/* XXX: this was taken from x86, now it's completely random. Luckily only
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* affects SMP padding. */
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# define L1_CACHE_SHIFT 5
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#endif
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