/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _SPARC64_ESTATE_H
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#define _SPARC64_ESTATE_H
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/* UltraSPARC-III E-cache Error Enable */
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#define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */
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#define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */
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#define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */
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#define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */
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#define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */
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#define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */
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#define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */
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/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
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* errors 2) uncorrectable E-cache errors. Such events only occur on reads
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* of the E-cache by the local processor for: 1) data loads 2) instruction
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* fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge
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* 2) writeback 2) copyout. The AFSR bits associated with these traps are
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* UCC and UCU.
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*/
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/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
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* for uncorrectable ECC errors and system errors.
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*
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* Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
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* or system bus BusERR:
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* 1) As the result of an instruction fetch, will generate instruction_access_error
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* 2) As the result of a load etc. will generate data_access_error.
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* 3) As the result of store merge completion, writeback, or copyout will
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* generate a disrupting ECC_error trap.
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* 4) As the result of such errors on instruction vector fetch can generate any
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* of the 3 trap types.
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*
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* The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
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* BERR, and TO.
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*/
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/* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus
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* reads resulting in a hardware corrected data or MTAG ECC error will generate an
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* ECC_error disrupting trap with this bit enabled.
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*
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* This same trap will also be generated when a hardware corrected ECC error results
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* during store merge, writeback, and copyout operations.
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*/
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/* In general, if the trap enable bits above are disabled the AFSR bits will still
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* log the events even though the trap will not be generated by the processor.
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*/
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#endif /* _SPARC64_ESTATE_H */
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