/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2005-2018 Andes Technology Corporation */
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#ifndef __NDS32_FPU_INST_H
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#define __NDS32_FPU_INST_H
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#define cop0_op 0x35
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/*
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* COP0 field of opcodes.
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*/
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#define fs1_op 0x0
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#define fs2_op 0x4
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#define fd1_op 0x8
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#define fd2_op 0xc
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/*
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* FS1 opcode.
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*/
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enum fs1 {
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fadds_op, fsubs_op, fcpynss_op, fcpyss_op,
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fmadds_op, fmsubs_op, fcmovns_op, fcmovzs_op,
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fnmadds_op, fnmsubs_op,
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fmuls_op = 0xc, fdivs_op,
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fs1_f2op_op = 0xf
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};
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/*
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* FS1/F2OP opcode.
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*/
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enum fs1_f2 {
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fs2d_op, fsqrts_op,
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fui2s_op = 0x8, fsi2s_op = 0xc,
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fs2ui_op = 0x10, fs2ui_z_op = 0x14,
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fs2si_op = 0x18, fs2si_z_op = 0x1c
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};
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/*
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* FS2 opcode.
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*/
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enum fs2 {
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fcmpeqs_op, fcmpeqs_e_op, fcmplts_op, fcmplts_e_op,
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fcmples_op, fcmples_e_op, fcmpuns_op, fcmpuns_e_op
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};
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/*
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* FD1 opcode.
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*/
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enum fd1 {
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faddd_op, fsubd_op, fcpynsd_op, fcpysd_op,
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fmaddd_op, fmsubd_op, fcmovnd_op, fcmovzd_op,
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fnmaddd_op, fnmsubd_op,
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fmuld_op = 0xc, fdivd_op, fd1_f2op_op = 0xf
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};
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/*
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* FD1/F2OP opcode.
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*/
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enum fd1_f2 {
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fd2s_op, fsqrtd_op,
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fui2d_op = 0x8, fsi2d_op = 0xc,
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fd2ui_op = 0x10, fd2ui_z_op = 0x14,
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fd2si_op = 0x18, fd2si_z_op = 0x1c
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};
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/*
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* FD2 opcode.
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*/
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enum fd2 {
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fcmpeqd_op, fcmpeqd_e_op, fcmpltd_op, fcmpltd_e_op,
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fcmpled_op, fcmpled_e_op, fcmpund_op, fcmpund_e_op
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};
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#define NDS32Insn(x) x
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#define I_OPCODE_off 25
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#define NDS32Insn_OPCODE(x) (NDS32Insn(x) >> I_OPCODE_off)
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#define I_OPCODE_offRt 20
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#define I_OPCODE_mskRt (0x1fUL << I_OPCODE_offRt)
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#define NDS32Insn_OPCODE_Rt(x) \
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((NDS32Insn(x) & I_OPCODE_mskRt) >> I_OPCODE_offRt)
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#define I_OPCODE_offRa 15
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#define I_OPCODE_mskRa (0x1fUL << I_OPCODE_offRa)
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#define NDS32Insn_OPCODE_Ra(x) \
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((NDS32Insn(x) & I_OPCODE_mskRa) >> I_OPCODE_offRa)
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#define I_OPCODE_offRb 10
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#define I_OPCODE_mskRb (0x1fUL << I_OPCODE_offRb)
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#define NDS32Insn_OPCODE_Rb(x) \
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((NDS32Insn(x) & I_OPCODE_mskRb) >> I_OPCODE_offRb)
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#define I_OPCODE_offbit1014 10
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#define I_OPCODE_mskbit1014 (0x1fUL << I_OPCODE_offbit1014)
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#define NDS32Insn_OPCODE_BIT1014(x) \
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((NDS32Insn(x) & I_OPCODE_mskbit1014) >> I_OPCODE_offbit1014)
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#define I_OPCODE_offbit69 6
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#define I_OPCODE_mskbit69 (0xfUL << I_OPCODE_offbit69)
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#define NDS32Insn_OPCODE_BIT69(x) \
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((NDS32Insn(x) & I_OPCODE_mskbit69) >> I_OPCODE_offbit69)
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#define I_OPCODE_offCOP0 0
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#define I_OPCODE_mskCOP0 (0x3fUL << I_OPCODE_offCOP0)
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#define NDS32Insn_OPCODE_COP0(x) \
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((NDS32Insn(x) & I_OPCODE_mskCOP0) >> I_OPCODE_offCOP0)
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#endif /* __NDS32_FPU_INST_H */
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