/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Memory barrier definitions. This is based on information published
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* in the Processor Abstraction Layer and the System Abstraction Layer
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* manual.
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*
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* Copyright (C) 1998-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
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* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
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*/
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#ifndef _ASM_IA64_BARRIER_H
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#define _ASM_IA64_BARRIER_H
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#include <linux/compiler.h>
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/*
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* Macros to force memory ordering. In these descriptions, "previous"
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* and "subsequent" refer to program order; "visible" means that all
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* architecturally visible effects of a memory access have occurred
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* (at a minimum, this means the memory has been read or written).
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*
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* wmb(): Guarantees that all preceding stores to memory-
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* like regions are visible before any subsequent
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* stores and that all following stores will be
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* visible only after all previous stores.
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* rmb(): Like wmb(), but for reads.
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* mb(): wmb()/rmb() combo, i.e., all previous memory
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* accesses are visible before all subsequent
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* accesses and vice versa. This is also known as
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* a "fence."
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*
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* Note: "mb()" and its variants cannot be used as a fence to order
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* accesses to memory mapped I/O registers. For that, mf.a needs to
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* be used. However, we don't want to always use mf.a because (a)
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* it's (presumably) much slower than mf and (b) mf.a is supported for
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* sequential memory pages only.
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*/
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#define mb() ia64_mf()
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#define rmb() mb()
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#define wmb() mb()
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#define dma_rmb() mb()
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#define dma_wmb() mb()
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# define __smp_mb() mb()
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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/*
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* IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no
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* need for asm trickery!
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*/
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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/*
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* The group barrier in front of the rsm & ssm are necessary to ensure
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* that none of the previous instructions in the same group are
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* affected by the rsm/ssm.
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*/
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#include <asm-generic/barrier.h>
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#endif /* _ASM_IA64_BARRIER_H */
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