; SPDX-License-Identifier: GPL-2.0-only
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;
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; Port on Texas Instruments TMS320C6x architecture
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;
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; Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
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; Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
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;
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; This section handles all the interrupt vector routines.
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; At RESET the processor sets up the DRAM timing parameters and
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; branches to the label _c_int00 which handles initialization for the C code.
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;
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#define ALIGNMENT 5
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.macro IRQVEC name, handler
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.align ALIGNMENT
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.hidden \name
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.global \name
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\name:
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#ifdef CONFIG_C6X_BIG_KERNEL
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STW .D2T1 A0,*B15--[2]
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|| MVKL .S1 \handler,A0
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MVKH .S1 \handler,A0
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B .S2X A0
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LDW .D2T1 *++B15[2],A0
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NOP 4
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NOP
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NOP
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.endm
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#else /* CONFIG_C6X_BIG_KERNEL */
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B .S2 \handler
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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.endm
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#endif /* CONFIG_C6X_BIG_KERNEL */
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.sect ".vectors","ax"
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.align ALIGNMENT
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.global RESET
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.hidden RESET
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RESET:
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#ifdef CONFIG_C6X_BIG_KERNEL
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MVKL .S1 _c_int00,A0 ; branch to _c_int00
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MVKH .S1 _c_int00,A0
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B .S2X A0
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#else
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B .S2 _c_int00
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NOP
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NOP
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#endif
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NOP
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NOP
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NOP
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NOP
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NOP
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IRQVEC NMI,_nmi_handler ; NMI interrupt
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IRQVEC AINT,_bad_interrupt ; reserved
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IRQVEC MSGINT,_bad_interrupt ; reserved
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IRQVEC INT4,_int4_handler
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IRQVEC INT5,_int5_handler
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IRQVEC INT6,_int6_handler
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IRQVEC INT7,_int7_handler
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IRQVEC INT8,_int8_handler
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IRQVEC INT9,_int9_handler
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IRQVEC INT10,_int10_handler
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IRQVEC INT11,_int11_handler
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IRQVEC INT12,_int12_handler
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IRQVEC INT13,_int13_handler
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IRQVEC INT14,_int14_handler
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IRQVEC INT15,_int15_handler
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