/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* TI DaVinci clock definitions
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*/
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#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
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#define __ARCH_ARM_DAVINCI_CLOCK_H
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/* PLL/Reset register offsets */
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#define PLLCTL 0x100
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#define PLLCTL_PLLEN BIT(0)
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#define PLLCTL_PLLPWRDN BIT(1)
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#define PLLCTL_PLLRST BIT(3)
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#define PLLCTL_PLLDIS BIT(4)
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#define PLLCTL_PLLENSRC BIT(5)
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#define PLLCTL_CLKMODE BIT(8)
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#define PLLM 0x110
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#define PLLM_PLLM_MASK 0xff
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#define PREDIV 0x114
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#define PLLDIV1 0x118
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#define PLLDIV2 0x11c
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#define PLLDIV3 0x120
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#define POSTDIV 0x128
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#define BPDIV 0x12c
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#define PLLCMD 0x138
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#define PLLSTAT 0x13c
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#define PLLALNCTL 0x140
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#define PLLDCHANGE 0x144
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#define PLLCKEN 0x148
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#define PLLCKSTAT 0x14c
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#define PLLSYSTAT 0x150
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#define PLLDIV4 0x160
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#define PLLDIV5 0x164
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#define PLLDIV6 0x168
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#define PLLDIV7 0x16c
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#define PLLDIV8 0x170
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#define PLLDIV9 0x174
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#define PLLDIV_EN BIT(15)
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#define PLLDIV_RATIO_MASK 0x1f
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/*
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* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
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* cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
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* ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
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* is ~25MHz. Units are micro seconds.
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*/
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#define PLL_BYPASS_TIME 1
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/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
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#define PLL_RESET_TIME 1
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/*
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* From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
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* Units are micro seconds.
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*/
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#define PLL_LOCK_TIME 20
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#endif
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